(no commit message)

[libreriscv.git] / index.mdwn

diff --git a/index.mdwn b/index.mdwn
index e9496b00bab8faaec0df592f70d2d0f19e525c98..f9806a84fb36066ea65ea934b11977cbc07c624c 100644 (file)
--- a/index.mdwn
+++ b/index.mdwn
@@ -63,6 +63,7 @@ We are proud of our talented and diverse [team](about_us).
   resources in Emerging markets, for completion of NLNet-funded tasks.
   See the upcoming [Hackathon](https://www.youtube.com/embed/Px6eakWja3Q"),
   deadline May 15th
   resources in Emerging markets, for completion of NLNet-funded tasks.
   See the upcoming [Hackathon](https://www.youtube.com/embed/Px6eakWja3Q"),
   deadline May 15th

+* The [[PowerPC Notebook]] Project

 
 # How Can I Help?
 
 
 # How Can I Help?
 


@@ -80,27 +81,28 @@ below.  If there is anything else,
 just get in touch on the list, there is plenty to do.
 
 1. First, join the
 just get in touch on the list, there is plenty to do.
 
 1. First, join the

-[mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev),
-introduce yourself (people will happily say "hello" back"). Read through
-[recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/)
-and the [[charter]], and let everyone know, on the list that you're
-happy with it and agree to it.
-2. The next thing you should do is read through the [bugs
-list](http://bugs.libre-riscv.org) and see if there are any bugs that
-pique your interest.  A fascinating way to do that is to view the
-[dependency graph](https://bugs.libre-soc.org/showdependencygraph.cgi?id=1&display=web&rankdir=LR)
-3. After that, go ahead and take a look at the    [git repositories](https://git.libre-riscv.org).
-
+  [mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev),
+  introduce yourself (people will happily say "hello" back"). Read through
+  [recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/)
+  and the [[charter]], and let everyone know, on the list that you're
+  happy with it and agree to it.
+2. The next thing you should do is read through the
+  [bugs list](http://bugs.libre-riscv.org) and
+  see if there are any bugs that pique your interest.
+  A fascinating way to do that is to view the
+  [dependency graph](https://bugs.libre-soc.org/showdependencygraph.cgi?id=1&display=web&rankdir=LR)
+3. After that, go ahead and take a look at the
+   [git repositories](https://git.libre-riscv.org).

 4. If you plan to do HDL work, you should familiarize yourself with our
 4. If you plan to do HDL work, you should familiarize yourself with our

-   [[HDL_workflow]].  If you would like to help with the ASIC layout,
-   see [[HDL_workflow/coriolis2]]
+  [[HDL_workflow]].  If you would like to help with the ASIC layout,
+  see [[HDL_workflow/coriolis2]]

 5. We do have funding available (see [[nlnet]]) upon completion of issues -
 5. We do have funding available (see [[nlnet]]) upon completion of issues -

-we are also working on procuring more funding which gets the project to
-nanometre scale tapeout.
+  we are also working on procuring more funding which gets the project to
+  nanometre scale tapeout.

 6. After all this, if you feel that Libre-SOC is a something
 6. After all this, if you feel that Libre-SOC is a something

-   that you would like to contribute to, add yourself to the
-   [current_members](about_us) page, fill in some information about yourself,
-   and join the mailing list and say hello.
+  that you would like to contribute to, add yourself to the
+  [current_members](about_us) page, fill in some information about yourself,
+  and join the mailing list and say hello.

 
 Also note that you can edit this wiki.  You can experiment in the [[Sandbox]].
 
 
 Also note that you can edit this wiki.  You can experiment in the [[Sandbox]].
 


@@ -114,19 +116,17 @@ Here is an example process of how to play with the soc code:
     source ~/.virtualenvs/libresoc/bin/activate
     
     cd ~; mkdir libresoc; cd libresoc
     source ~/.virtualenvs/libresoc/bin/activate
     
     cd ~; mkdir libresoc; cd libresoc

-    git clone https://git.libre-riscv.org/git/nmutil.git
-    git clone https://git.libre-riscv.org/git/ieee754fpu.git
-    git clone https://git.libre-riscv.org/git/soc.git
+    git clone https://git.libre-soc.org/git/nmutil.git
+    git clone https://git.libre-soc.org/git/ieee754fpu.git
+    git clone https://git.libre-soc.org/git/soc.git

     
     

-    cd nmutil; pip3 install -e .; cd ..
-    cd ieee754fpu; pip3 install -e .; cd ..
-    cd soc; git submodule init; git submodule update; pip3 install -e .; cd ..
+    cd nmutil; make install; cd ..
+    cd ieee754fpu; make install; cd ..
+    cd soc; make gitupdate; make install; cd ..

     
     python3 soc/src/soc/decoder/power_decoder.py
     yosys -p "read_ilang decoder.il; show dec31" 
 
     
     python3 soc/src/soc/decoder/power_decoder.py
     yosys -p "read_ilang decoder.il; show dec31" 
 

-
-

 ## How can I learn?
 
 The whole purpose of this project is to be a learning environment as well
 ## How can I learn?
 
 The whole purpose of this project is to be a learning environment as well


@@ -160,4 +160,7 @@ accelerated opcodes (all of which SwiftShader lacks)
 Also, individuals with experience in formal mathematical verification
 are quite welcome.
 
 Also, individuals with experience in formal mathematical verification
 are quite welcome.
 

-# [Documentation](Documentation/SOC/index)
+# Documentation
+
+ - [Source Code](/Documentation/index)
+ - [Architecture](3d_gpu/architecture)