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add mvendor/march WARL update
[libreriscv.git]
/
isa_conflict_resolution.mdwn
diff --git
a/isa_conflict_resolution.mdwn
b/isa_conflict_resolution.mdwn
index 2eaee64703aeb7ef7105f25daaaaf29933b40506..6d11681eb4f862b607a2afb6193d0973c79954f4 100644
(file)
--- a/
isa_conflict_resolution.mdwn
+++ b/
isa_conflict_resolution.mdwn
@@
-267,7
+267,7
@@
turn the custom instruction into an actual binary-encoding (plus
binary-encoding of the context-switching information). (**TBD, Jacob,
separate page? review this para?**)
binary-encoding of the context-switching information). (**TBD, Jacob,
separate page? review this para?**)
-# mvendorid/marchid WARL <a name="
#
mvendor_marchid_warl"></a>
+# mvendorid/marchid WARL <a name="mvendor_marchid_warl"></a>
(Summary: the only idea that meets the full requirements. Needs
toolchain backup, but only when the first chip is released)
(Summary: the only idea that meets the full requirements. Needs
toolchain backup, but only when the first chip is released)
@@
-358,7
+358,7
@@
Update 29apr2018:
hardware-level ISA support to not be permitted to receive RISC-V
Certification Compliance.
hardware-level ISA support to not be permitted to receive RISC-V
Certification Compliance.
-# ioctl-like <a name="
#
ioctl-like"></a>
+# ioctl-like <a name="ioctl-like"></a>
(Summary: good solid orthogonal idea. See [[ioctl]] for full details)
(Summary: good solid orthogonal idea. See [[ioctl]] for full details)