+ else if (cell->type == ID($bmux))
+ {
+ if (!eval(sig_s, undef, cell))
+ return false;
+
+ if (sig_s.is_fully_def()) {
+ int sel = sig_s.as_int();
+ int width = GetSize(sig_y);
+ SigSpec res = sig_a.extract(sel * width, width);
+ if (!eval(res, undef, cell))
+ return false;
+ set(sig_y, res.as_const());
+ } else {
+ if (!eval(sig_a, undef, cell))
+ return false;
+ set(sig_y, const_bmux(sig_a.as_const(), sig_s.as_const()));
+ }
+ }
+ else if (cell->type == ID($demux))
+ {
+ if (!eval(sig_a, undef, cell))
+ return false;
+ if (sig_a.is_fully_zero()) {
+ set(sig_y, Const(0, GetSize(sig_y)));
+ } else {
+ if (!eval(sig_s, undef, cell))
+ return false;
+ set(sig_y, const_demux(sig_a.as_const(), sig_s.as_const()));
+ }
+ }
+ else if (cell->type == ID($fa))
+ {
+ RTLIL::SigSpec sig_c = cell->getPort(ID::C);
+ RTLIL::SigSpec sig_x = cell->getPort(ID::X);
+ int width = GetSize(sig_c);
+
+ if (!eval(sig_a, undef, cell))
+ return false;
+
+ if (!eval(sig_b, undef, cell))
+ return false;
+
+ if (!eval(sig_c, undef, cell))
+ return false;
+
+ RTLIL::Const t1 = const_xor(sig_a.as_const(), sig_b.as_const(), false, false, width);
+ RTLIL::Const val_y = const_xor(t1, sig_c.as_const(), false, false, width);
+
+ RTLIL::Const t2 = const_and(sig_a.as_const(), sig_b.as_const(), false, false, width);
+ RTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width);
+ RTLIL::Const val_x = const_or(t2, t3, false, false, width);
+
+ for (int i = 0; i < GetSize(val_y); i++)
+ if (val_y.bits[i] == RTLIL::Sx)
+ val_x.bits[i] = RTLIL::Sx;
+
+ set(sig_y, val_y);
+ set(sig_x, val_x);
+ }
+ else if (cell->type == ID($alu))
+ {
+ bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
+ bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();
+
+ RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
+ RTLIL::SigSpec sig_bi = cell->getPort(ID::BI);
+
+ if (!eval(sig_a, undef, cell))
+ return false;
+
+ if (!eval(sig_b, undef, cell))
+ return false;
+
+ if (!eval(sig_ci, undef, cell))
+ return false;
+
+ if (!eval(sig_bi, undef, cell))
+ return false;
+
+ RTLIL::SigSpec sig_x = cell->getPort(ID::X);
+ RTLIL::SigSpec sig_co = cell->getPort(ID::CO);
+
+ bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());
+ sig_a.extend_u0(GetSize(sig_y), signed_a);
+ sig_b.extend_u0(GetSize(sig_y), signed_b);
+
+ bool carry = sig_ci[0] == State::S1;
+ bool b_inv = sig_bi[0] == State::S1;
+
+ for (int i = 0; i < GetSize(sig_y); i++)
+ {
+ RTLIL::SigSpec x_inputs = { sig_a[i], sig_b[i], sig_bi[0] };
+
+ if (!x_inputs.is_fully_def()) {
+ set(sig_x[i], RTLIL::Sx);
+ } else {
+ bool bit_a = sig_a[i] == State::S1;
+ bool bit_b = (sig_b[i] == State::S1) != b_inv;
+ bool bit_x = bit_a != bit_b;
+ set(sig_x[i], bit_x ? State::S1 : State::S0);
+ }
+
+ if (any_input_undef) {
+ set(sig_y[i], RTLIL::Sx);
+ set(sig_co[i], RTLIL::Sx);
+ } else {
+ bool bit_a = sig_a[i] == State::S1;
+ bool bit_b = (sig_b[i] == State::S1) != b_inv;
+ bool bit_y = (bit_a != bit_b) != carry;
+ carry = (bit_a && bit_b) || (bit_a && carry) || (bit_b && carry);
+ set(sig_y[i], bit_y ? State::S1 : State::S0);
+ set(sig_co[i], carry ? State::S1 : State::S0);
+ }
+ }
+ }
+ else if (cell->type == ID($macc))
+ {
+ Macc macc;
+ macc.from_cell(cell);
+
+ if (!eval(macc.bit_ports, undef, cell))
+ return false;
+
+ for (auto &port : macc.ports) {
+ if (!eval(port.in_a, undef, cell))
+ return false;
+ if (!eval(port.in_b, undef, cell))
+ return false;
+ }
+
+ RTLIL::Const result(0, GetSize(cell->getPort(ID::Y)));
+ if (!macc.eval(result))
+ log_abort();
+
+ set(cell->getPort(ID::Y), result);
+ }