+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ bool scriptwire = false;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++) {
+ if (args[argidx] == "-scriptwire") {
+ scriptwire = true;
+ continue;
+ }
+ break;
+ }
+ if (scriptwire) {
+ extra_args(args, argidx, design);
+
+ for (auto mod : design->selected_modules())
+ for (auto &c : mod->connections()) {
+ if (!c.first.is_wire())
+ continue;
+ auto w = c.first.as_wire();
+ if (!mod->selected(w))
+ continue;
+ if (!c.second.is_fully_const())
+ log_error("RHS of selected wire %s.%s is not constant.\n", log_id(mod), log_id(w));
+ auto v = c.second.as_const();
+ Pass::call_on_module(design, mod, v.decode_string());
+ }
+ }
+ else if (args.size() < 2)