-by 1bitsquared. however for the *four* IC HyperRAM PMOD, *four*
-separate and distinct instances are needed, each with a different
-cs_n pin. on the TODO list for this module: interleave multiple HyperRAM
-cs_n's to give striped (like RAID) memory accesses behind one single
-Wishbone interface.
+by 1bitsquared. however for the *four* IC HyperRAM PMOD, *four* cs_n pins
+are needed. These are then used to select, in turn, each IC, sequentially:
+ * Access to 0x00000-0xfffff will activate CS0n,
+ * Access to 0x100000-0x1fffff will activate CS1n,
+ * Access to 0x200000-0x2fffff will activate CS2n,
+ * Access to 0x300000-0x3fffff will activate CS3n
+
+TODO: interleave multiple HyperRAM cs_n's to give striped (like RAID)
+memory accesses behind one single Wishbone interface.
+TODO: investigate whether HyperBUS can do CSn-striping in hardware
+(it should do, but this will require configuration registers to be written)