+ req := '0';
+ mmu_mtspr := '0';
+ itlb_fault := '0';
+ sprn := std_ulogic_vector(to_unsigned(decode_spr_num(l_in.insn), 10));
+ dsisr := (others => '0');
+ mmureq := '0';
+ v.wr_sel := "11";
+
+ write_enable := '0';
+
+ do_update := r.do_update;
+ v.do_update := '0';
+
+ -- load data formatting
+ -- shift and byte-reverse data bytes
+ for i in 0 to 7 loop
+ j := to_integer(r.byte_index(i)) * 8;
+ data_permuted(i * 8 + 7 downto i * 8) := d_in.data(j + 7 downto j);
+ end loop;
+
+ -- Work out the sign bit for sign extension.
+ -- For unaligned loads crossing two dwords, the sign bit is in the
+ -- first dword for big-endian (byte_reverse = 1), or the second dword
+ -- for little-endian.
+ if r.dwords_done = '1' and r.byte_reverse = '1' then
+ negative := (r.length(3) and r.load_data(63)) or
+ (r.length(2) and r.load_data(31)) or
+ (r.length(1) and r.load_data(15)) or
+ (r.length(0) and r.load_data(7));
+ else
+ negative := (r.length(3) and data_permuted(63)) or
+ (r.length(2) and data_permuted(31)) or
+ (r.length(1) and data_permuted(15)) or
+ (r.length(0) and data_permuted(7));
+ end if;
+
+ -- trim and sign-extend
+ for i in 0 to 7 loop
+ case r.trim_ctl(i) is
+ when "11" =>
+ data_trimmed(i * 8 + 7 downto i * 8) := r.load_data(i * 8 + 7 downto i * 8);
+ when "10" =>
+ data_trimmed(i * 8 + 7 downto i * 8) := data_permuted(i * 8 + 7 downto i * 8);
+ when "01" =>
+ data_trimmed(i * 8 + 7 downto i * 8) := (others => negative);
+ when others =>
+ data_trimmed(i * 8 + 7 downto i * 8) := x"00";
+ end case;
+ end loop;
+
+ if HAS_FPU then
+ -- Single-precision FP conversion for loads
+ v.ld_sp_data := data_trimmed(31 downto 0);
+ v.ld_sp_nz := or (data_trimmed(22 downto 0));
+ v.ld_sp_lz := count_left_zeroes(data_trimmed(22 downto 0));
+ end if;
+
+ -- Byte reversing and rotating for stores.
+ -- Done in the second cycle (the cycle after l_in.valid = 1).
+ for i in 0 to 7 loop
+ k := (to_unsigned(i, 3) - r.byte_offset) xor r.brev_mask;
+ j := to_integer(k) * 8;
+ store_data(i * 8 + 7 downto i * 8) := r.store_data(j + 7 downto j);
+ end loop;
+
+ -- compute (addr + 8) & ~7 for the second doubleword when unaligned
+ next_addr := std_ulogic_vector(unsigned(r.addr(63 downto 3)) + 1) & "000";
+
+ -- Busy calculation.
+ -- We need to minimize the delay from clock to busy valid because it
+ -- gates the start of execution of the next instruction.
+ busy := r.busy and not ((r.wait_dcache and d_in.valid) or (r.wait_mmu and m_in.done));
+ v.busy := busy;
+
+ done := '0';
+ if r.state /= IDLE and busy = '0' then
+ done := '1';
+ end if;
+ exception := '0';
+
+ if r.dwords_done = '1' or r.state = SECOND_REQ then
+ addr := next_addr;
+ byte_sel := r.second_bytes;
+ else
+ addr := r.addr;
+ byte_sel := r.first_bytes;
+ end if;
+ if r.mode_32bit = '1' then
+ addr(63 downto 32) := (others => '0');
+ end if;
+ maddr := addr;
+
+ case r.state is
+ when IDLE =>
+
+ when SECOND_REQ =>
+ req := '1';
+ v.state := ACK_WAIT;
+ v.last_dword := '0';
+
+ when ACK_WAIT =>
+ -- r.wr_sel gets set one cycle after we come into ACK_WAIT state,
+ -- which is OK because the dcache always takes at least two cycles.
+ if r.update = '1' and (r.load = '0' or (HAS_FPU and r.load_sp = '1')) then
+ v.wr_sel := "01";
+ end if;
+ if d_in.error = '1' then
+ -- dcache will discard the second request if it
+ -- gets an error on the 1st of two requests
+ if d_in.cache_paradox = '1' then
+ -- signal an interrupt straight away
+ exception := '1';
+ dsisr(63 - 38) := not r.load;
+ -- XXX there is no architected bit for this
+ dsisr(63 - 35) := d_in.cache_paradox;
+ else
+ -- Look up the translation for TLB miss
+ -- and also for permission error and RC error
+ -- in case the PTE has been updated.
+ mmureq := '1';
+ v.state := MMU_LOOKUP;
+ end if;
+ end if;
+ if d_in.valid = '1' then
+ if r.last_dword = '0' then
+ v.dwords_done := '1';
+ v.last_dword := '1';
+ if r.load = '1' then
+ v.load_data := data_permuted;
+ end if;
+ else
+ write_enable := r.load and not r.load_sp;
+ if HAS_FPU and r.load_sp = '1' then
+ -- SP to DP conversion takes a cycle
+ -- Write back rA update in this cycle if needed
+ do_update := r.update;
+ v.wr_sel := "10";
+ v.state := FINISH_LFS;
+ elsif r.extra_cycle = '1' then
+ -- loads with rA update need an extra cycle
+ v.wr_sel := "01";
+ v.state := COMPLETE;
+ v.do_update := r.update;
+ else
+ -- stores write back rA update in this cycle
+ do_update := r.update;
+ end if;
+ v.busy := '0';
+ end if;
+ end if;
+ -- r.wait_dcache gets set one cycle after we come into ACK_WAIT state,
+ -- which is OK because the dcache always takes at least two cycles.
+ v.wait_dcache := r.last_dword and not r.extra_cycle;
+
+ when MMU_LOOKUP =>
+ if m_in.done = '1' then
+ if r.instr_fault = '0' then
+ -- retry the request now that the MMU has installed a TLB entry
+ req := '1';
+ if r.last_dword = '0' then
+ v.state := SECOND_REQ;
+ else
+ v.state := ACK_WAIT;
+ end if;
+ end if;
+ end if;
+ if m_in.err = '1' then
+ exception := '1';
+ dsisr(63 - 33) := m_in.invalid;
+ dsisr(63 - 36) := m_in.perm_error;
+ dsisr(63 - 38) := not r.load;
+ dsisr(63 - 44) := m_in.badtree;
+ dsisr(63 - 45) := m_in.rc_error;
+ end if;
+
+ when TLBIE_WAIT =>
+
+ when FINISH_LFS =>
+
+ when COMPLETE =>
+ exception := r.align_intr;
+
+ end case;
+
+ if done = '1' or exception = '1' then
+ v.state := IDLE;
+ v.busy := '0';
+ end if;
+
+ -- Note that l_in.valid is gated with busy inside execute1
+ if l_in.valid = '1' then
+ v.mode_32bit := l_in.mode_32bit;
+ v.load := '0';
+ v.dcbz := '0';
+ v.tlbie := '0';
+ v.instr_fault := '0';
+ v.align_intr := '0';
+ v.dwords_done := '0';
+ v.last_dword := '1';
+ v.write_reg := l_in.write_reg;
+ v.length := l_in.length;
+ v.byte_reverse := l_in.byte_reverse;
+ v.sign_extend := l_in.sign_extend;
+ v.update := l_in.update;
+ v.update_reg := l_in.update_reg;
+ v.xerc := l_in.xerc;
+ v.reserve := l_in.reserve;
+ v.rc := l_in.rc;
+ v.nc := l_in.ci;
+ v.virt_mode := l_in.virt_mode;
+ v.priv_mode := l_in.priv_mode;
+ v.load_sp := '0';
+ v.wait_dcache := '0';
+ v.wait_mmu := '0';
+ v.do_update := '0';
+ v.extra_cycle := '0';
+
+ if HAS_FPU and l_in.is_32bit = '1' then
+ v.store_data := x"00000000" & store_sp_data;
+ else
+ v.store_data := l_in.data;
+ end if;
+
+ addr := lsu_sum;
+ if l_in.second = '1' then
+ -- for the second half of a 16-byte transfer, use next_addr
+ addr := next_addr;
+ end if;
+ if l_in.mode_32bit = '1' then
+ addr(63 downto 32) := (others => '0');
+ end if;
+ v.addr := addr;
+ maddr := l_in.addr2; -- address from RB for tlbie
+
+ -- XXX Temporary hack. Mark the op as non-cachable if the address
+ -- is the form 0xc------- for a real-mode access.
+ if addr(31 downto 28) = "1100" and l_in.virt_mode = '0' then
+ v.nc := '1';
+ end if;
+
+ if l_in.second = '0' then
+ -- Do length_to_sel and work out if we are doing 2 dwords
+ long_sel := xfer_data_sel(l_in.length, lsu_sum(2 downto 0));
+ byte_sel := long_sel(7 downto 0);
+ v.first_bytes := byte_sel;
+ v.second_bytes := long_sel(15 downto 8);
+ else
+ byte_sel := r.first_bytes;
+ long_sel := r.second_bytes & r.first_bytes;
+ end if;
+
+ -- check alignment for larx/stcx
+ misaligned := or (std_ulogic_vector(unsigned(l_in.length(2 downto 0)) - 1) and addr(2 downto 0));
+ v.align_intr := l_in.reserve and misaligned;
+ if l_in.repeat = '1' and l_in.second = '0' and addr(3) = '1' then
+ -- length is really 16 not 8
+ -- Make misaligned lq cause an alignment interrupt in LE mode,
+ -- in order to avoid the case with RA = RT + 1 where the second half
+ -- faults but the first doesn't (and updates RT+1, destroying RA).
+ -- The equivalent BE case doesn't occur because RA = RT is illegal.
+ misaligned := '1';
+ if l_in.reserve = '1' or (l_in.op = OP_LOAD and l_in.byte_reverse = '0') then
+ v.align_intr := '1';
+ end if;
+ end if;
+
+ v.atomic := not misaligned;
+ v.atomic_last := not misaligned and (l_in.second or not l_in.repeat);
+
+ case l_in.op is
+ when OP_STORE =>
+ req := '1';
+ when OP_LOAD =>
+ req := '1';
+ v.load := '1';
+ -- Allow an extra cycle for RA update on loads
+ v.extra_cycle := l_in.update;
+ if HAS_FPU and l_in.is_32bit = '1' then
+ -- Allow an extra cycle for SP->DP precision conversion
+ v.load_sp := '1';
+ v.extra_cycle := '1';
+ end if;
+ when OP_DCBZ =>
+ v.align_intr := v.nc;
+ req := '1';
+ v.dcbz := '1';
+ when OP_TLBIE =>
+ mmureq := '1';
+ v.tlbie := '1';
+ v.state := TLBIE_WAIT;
+ v.wait_mmu := '1';
+ when OP_MFSPR =>
+ v.wr_sel := "00";
+ -- partial decode on SPR number should be adequate given
+ -- the restricted set that get sent down this path
+ if sprn(9) = '0' and sprn(5) = '0' then
+ if sprn(0) = '0' then
+ v.sprval := x"00000000" & r.dsisr;
+ else
+ v.sprval := r.dar;
+ end if;
+ else
+ -- reading one of the SPRs in the MMU
+ v.sprval := m_in.sprval;
+ end if;
+ v.state := COMPLETE;
+ when OP_MTSPR =>
+ if sprn(9) = '0' and sprn(5) = '0' then
+ if sprn(0) = '0' then
+ v.dsisr := l_in.data(31 downto 0);
+ else
+ v.dar := l_in.data;
+ end if;
+ v.state := COMPLETE;
+ else
+ -- writing one of the SPRs in the MMU
+ mmu_mtspr := '1';
+ v.state := TLBIE_WAIT;
+ v.wait_mmu := '1';
+ end if;
+ when OP_FETCH_FAILED =>
+ -- send it to the MMU to do the radix walk
+ maddr := l_in.nia;
+ v.instr_fault := '1';
+ mmureq := '1';
+ v.state := MMU_LOOKUP;
+ v.wait_mmu := '1';
+ when others =>
+ assert false report "unknown op sent to loadstore1";
+ end case;