- # Emulator / Pads
- sdcard_pads = self.cpu.cpupads['sd0']
-
- # Core
- self.submodules.sdphy = SDPHY(sdcard_pads,
- self.platform.device, self.clk_freq)
- self.submodules.sdcore = SDCore(self.sdphy)
- self.add_csr("sdphy")
- self.add_csr("sdcore")
-
- # Block2Mem DMA
- bus = wishbone.Interface(data_width=self.bus.data_width,
- adr_width=self.bus.address_width)
- self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus,
- endianness=self.cpu.endianness)
- self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
- dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
- dma_bus.add_master("sdblock2mem", master=bus)
- self.add_csr("sdblock2mem")
-
- # Mem2Block DMA
- bus = wishbone.Interface(data_width=self.bus.data_width,
- adr_width=self.bus.address_width)
- self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus,
- endianness=self.cpu.endianness)
- self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
- dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
- dma_bus.add_master("sdmem2block", master=bus)
- self.add_csr("sdmem2block")
+ if hasattr(self.cpu.cpupads, 'sd0'):
+ # Emulator / Pads
+ sdcard_pads = self.cpu.cpupads['sd0']
+
+ # Core
+ self.submodules.sdphy = SDPHY(sdcard_pads,
+ self.platform.device, self.clk_freq)
+ self.submodules.sdcore = SDCore(self.sdphy)
+ self.add_csr("sdphy")
+ self.add_csr("sdcore")
+
+ # Block2Mem DMA
+ bus = wishbone.Interface(data_width=self.bus.data_width,
+ adr_width=self.bus.address_width)
+ self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus,
+ endianness=self.cpu.endianness)
+ self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
+ dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
+ dma_bus.add_master("sdblock2mem", master=bus)
+ self.add_csr("sdblock2mem")
+
+ # Mem2Block DMA
+ bus = wishbone.Interface(data_width=self.bus.data_width,
+ adr_width=self.bus.address_width)
+ self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus,
+ endianness=self.cpu.endianness)
+ self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
+ dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
+ dma_bus.add_master("sdmem2block", master=bus)
+ self.add_csr("sdmem2block")