bug 1034: making room for crfbinlog/crfternlogi/crbinlog/crternlogi

[libreriscv.git] / nlnet_2019_coriolis2.mdwn

diff --git a/nlnet_2019_coriolis2.mdwn b/nlnet_2019_coriolis2.mdwn
index 11cefa8cc8d933e653d4802ce25464535c0819e1..a3f298bfb1a50f90338439ed150da862ec4077b1 100644 (file)
--- a/nlnet_2019_coriolis2.mdwn
+++ b/nlnet_2019_coriolis2.mdwn
@@ -1,12 +1,19 @@
-# NL.net proposal
+# NLnet.net LIP6.fr Coriolis2 proposal
+
+* [[questions]]
+* approved 20dec2019
+* MOU done
+* 2019-10-029
+* NLNet Project Page <https://nlnet.nl/project/Coriolis2/>
+* Top-level bugreport <http://bugs.libre-riscv.org/show_bug.cgi?id=138>

 
 ## Project name
 
 
 ## Project name
 

-The Libre-RISCV SoC, Coriolis2 ASIC Layout Collaboration
+Libre-SoC, Coriolis2 ASIC Layout Collaboration

 
 ## Website / wiki 
 
 
 ## Website / wiki 
 

-<https://libre-riscv.org/nlnet_2019_coriolis2>
+<https://libre-soc.org/nlnet_2019_coriolis2>

 
 Please be short and to the point in your answers; focus primarily on
 the what and how, not so much on the why. Add longer descriptions as
 
 Please be short and to the point in your answers; focus primarily on
 the what and how, not so much on the why. Add longer descriptions as


@@ -29,10 +36,10 @@ It is necessary, therefore, to use libre-licensed VLSI Layout tools
 rather than pay for proprietary software that, apart from being incredibly
 expensive, could potentially compromise the integrity of the project.
 
 rather than pay for proprietary software that, apart from being incredibly
 expensive, could potentially compromise the integrity of the project.
 

-We therefore intend to collaborate with engineers from the Laboratoire
-d'Informatique de Paris 6, to use and improve their VLSI Layout tool,
-Coriolis2, in conjunction with Chips4Makers, to create the layout that
-Chips4Makers will then put into a 180nm 300mhz test chip.
+We therefore intend to collaborate with engineers from LIP6, to use
+and improve their VLSI Layout tool, Coriolis2, in conjunction with
+Chips4Makers, to create the layout that Chips4Makers will then put into
+a 180nm 300mhz test chip.

 
 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
 
 
 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
 


@@ -42,8 +49,7 @@ Luke Leighton is an ethical technology specialist who has a consistent
 lead developer on the Libre RISC-V SoC.
 
 Jean-Paul Chaput is the lead engineer on the Alliance and Coriolis2
 lead developer on the Libre RISC-V SoC.
 
 Jean-Paul Chaput is the lead engineer on the Alliance and Coriolis2

-tools for VLSI backend layout, from the Laboratoire d'Informatique de
-Paris 6.
+tools for VLSI backend layout, from LIP6.

 
 # Requested Amount    
 
 
 # Requested Amount    
 


@@ -86,7 +92,7 @@ So therefore, the requested budget will be used for:
 * Essential augmentations to nmigen to make it ASIC-layout-capable
 
 All of these will be and are entirely libre-licensed software: there will
 * Essential augmentations to nmigen to make it ASIC-layout-capable
 
 All of these will be and are entirely libre-licensed software: there will

-be no proprietary software tools utilised in this process.  Note that
+be no proprietary software tools utilised in this process.

 
 
 # Does the project have other funding sources, both past and present?
 
 
 # Does the project have other funding sources, both past and present?