add opencl

[libreriscv.git] / nlnet_2019_coriolis2.mdwn

diff --git a/nlnet_2019_coriolis2.mdwn b/nlnet_2019_coriolis2.mdwn
index 158cbd075a30a025fc3464696d536ea21b260288..d558a609cb67f77e307c876aa253f7adcb1ec304 100644 (file)
--- a/nlnet_2019_coriolis2.mdwn
+++ b/nlnet_2019_coriolis2.mdwn
@@ -1,4 +1,11 @@
-# NL.net proposal
+# NLnet.net LIP6.fr Coriolis2 proposal
+
+* [[questions]]
+* approved 20dec2019
+* MOU TBD
+* 2019-10-029
+* NLNet Project Page <https://nlnet.nl/project/Coriolis2/>
+* Top-level bugreport <http://bugs.libre-riscv.org/show_bug.cgi?id=138>

 
 ## Project name
 
 
 ## Project name
 


@@ -29,10 +36,10 @@ It is necessary, therefore, to use libre-licensed VLSI Layout tools
 rather than pay for proprietary software that, apart from being incredibly
 expensive, could potentially compromise the integrity of the project.
 
 rather than pay for proprietary software that, apart from being incredibly
 expensive, could potentially compromise the integrity of the project.
 

-We therefore intend to collaborate with engineers from the Laboratoire
-d'Informatique de Paris 6, to use and improve their VLSI Layout tool,
-Coriolis2, in conjunction with Chips4Makers, to create the layout that
-Chips4Makers will then put into a 180nm 300mhz test chip.
+We therefore intend to collaborate with engineers from LIP6, to use
+and improve their VLSI Layout tool, Coriolis2, in conjunction with
+Chips4Makers, to create the layout that Chips4Makers will then put into
+a 180nm 300mhz test chip.

 
 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
 
 
 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
 


@@ -42,12 +49,11 @@ Luke Leighton is an ethical technology specialist who has a consistent
 lead developer on the Libre RISC-V SoC.
 
 Jean-Paul Chaput is the lead engineer on the Alliance and Coriolis2
 lead developer on the Libre RISC-V SoC.
 
 Jean-Paul Chaput is the lead engineer on the Alliance and Coriolis2

-tools for VLSI backend layout, from the Laboratoire d'Informatique de
-Paris 6.
+tools for VLSI backend layout, from LIP6.

 
 # Requested Amount    
 
 
 # Requested Amount    
 

-EUR $50,000.
+EUR 50,000.

 
 # Explain what the requested budget will be used for? 
 
 
 # Explain what the requested budget will be used for? 
 


@@ -86,30 +92,91 @@ So therefore, the requested budget will be used for:
 * Essential augmentations to nmigen to make it ASIC-layout-capable
 
 All of these will be and are entirely libre-licensed software: there will
 * Essential augmentations to nmigen to make it ASIC-layout-capable
 
 All of these will be and are entirely libre-licensed software: there will

-be no proprietary software tools utilised in this process.  Note that
+be no proprietary software tools utilised in this process.

 
 
 # Does the project have other funding sources, both past and present?
 
 
 
 # Does the project have other funding sources, both past and present?
 

+The overall project has sponsorship from Purism as well as a prior grant
+from NLNet.  However that is for specifically covering the development
+of the RTL (the hardware source code).
+
+There is no source of funds for the work on the *next* stage: the actual
+VLSI ASIC Layout.  Chips4Makers is however putting in an *additional*
+(and separate) funding application for the stage after *this*: the
+creation of the Cell Libraries that will be used in the VLSI ASIC Layout.
+
+All these three projects are separate and distinct (despite being related
+to the same CPU), and funding may not cross over from one project to
+the other.

 
 # Compare your own project with existing or historical efforts.
 
 
 # Compare your own project with existing or historical efforts.
 

+There are several Open VLSI Tool suites:
+
+* GNU Electric: https://www.gnu.org/software/electric/
+* MAGIC: http://opencircuitdesign.com/magic/
+* The OpenROAD Project: https://theopenroadproject.org/ (using MAGIC)
+* QFlow: http://opencircuitdesign.com/qflow/
+* Toped: http://www.toped.org.uk/
+
+and a few more.  We choose Coriolis2 because of its python interface.
+The VLSI Layout is actually done as a *python* program.  With nmigen
+(the HDL) being in python, we anticipate the same OO benefits to be
+achievable in coriolis2 as well.
+
+The case for the Libre RISC-V SoC itself was made already in the initial
+2018.02 proposal.  That has not changed: there are no Libre / Open Projects
+approaching anything like the complexity and product market opportunities
+of the Libre RISC-V SoC, which is being designed to be a quad-core 800mhz
+multi-issue out-of-order design.  All other Libre / Open processors such
+as Raven, and many more, have a goal set in advance not to exceed around
+the 350mhz mark, and are single-core.
+
+Other projects which are "open", such as the Ariane Processor, are
+developed by universities, and in the case of Ariane were *SPECIFICALLY*
+designed by and for the use of proprietary toolchains, such as those from
+Cadence, Synopsys and Mentor Graphics.  Despite the source code being
+"open", there was absolutely no expectation that the processor of the
+same capability as the Libre RISC-V SoC would use Libre / Open tools.
+
+Although our first ASIC (thanks to Chips4Makers) will be only 180nm,
+single-core and a maximum of around 350mhz, this is just the first
+stepping stone to a much larger processor.

 
 ## What are significant technical challenges you expect to solve during the project, if any?
 
 
 ## What are significant technical challenges you expect to solve during the project, if any?
 

+Some of these have been mentioned above:
+
+* NDAs by Foundries may interfere with the ability for Chips4Makers to
+  communicate with LIP6 regarding the necessary changes to NSXLIB which
+  meet the TSMC Foundry "Design Rule Checks" (DRCs).
+* Bugs or missing features in nmigen, yosys, coriolis2, NSXLIB, OpenRAM,
+  and the knock-on implications throughout the chain, right the way up
+  to the *actual* Libre RISC-V SoC's HDL source code itself, all need to
+  be dealt with.
+* Circuit simulation and unit testing is going to be a major factor, and
+  a huge utilisation of Computing power.  Machines with "only" 16 GB of RAM
+  and high-end quad-core processors are going to be hopelessly inadequate.

 
 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 
 
 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 

-We have a pre-launch Crowdsupply page up and running already, at
-https://www.crowdsupply.com/libre-risc-v/m-class through which we will
-engage with developers and end-users alike.  Developers will be invited
-to participate through the http://libre-riscv.org website and resources.
+LIP6 have their own mailing list for the (transparent) discussion of
+issues related to coriolis2: <alliance-users@asim.lip6.fr>.  The Libre RISC-V
+SoC has a full set of resources for Libre Project Management and development:
+mailing list, bugtracker, git repository and wiki - all listed here:
+<https://libre-riscv.org/>

 
 

-The Crowdsupply page has already been picked up by Phoronix, Heise.de
-Magazine, reddit and ycombinator.  There is a lot of interest in this
-project.
+In addition, we have a Crowdsupply page
+<https://www.crowdsupply.com/libre-risc-v/m-class> which provides a public
+gateway, and heise.de, reddit, phoronix, slashdot and other locations have
+all picked up the story.  The list is updated and maintained here:
+<https://libre-riscv.org/3d_gpu/>

 
 # Extra info to be submitted
 
 
 # Extra info to be submitted
 

-* <https://hardware.slashdot.org/story/18/12/11/1410200/super-micro-says-review-found-no-malicious-chips-in-motherboards>
-* <https://libreboot.org/faq.html#intelme>
+* <http://libre-riscv.org/3d_gpu/>
+* <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
+* <https://nlnet.nl/project/Libre-RISCV/>
+* <https://chips4makers.io/blog/>
+