-* Definition of assembler and disassembler and other binutil tools for RISC-V
- instructions and also SVP32, 48 and 64 in the Libre-SOC infrastructure.
-* Creation of test code routines based on output of previous POWER ISA projects
- (cryptoprimitives, codecs), and testing and validation of the binutils
+* Completion of libopid (an instruction database parser)
+* Completion of libopid porting of Libre-SOC infrastructure both Scalar Power ISA
+ and SVP64/Power (currently based on an early iteration of libopid)
+* Definition of assembler and disassembler for RISC-V
+ instructions and also SVP32, 48 and 64 Vector Prefixing formats, using libopid
+* Completion of definitions of Simple-V/Single formats SVP64Single, SVP48Singe and SVP32Single
+ and implementation support of the same for both Power and RISC-V
+ (https://libre-soc.org/openpower/sv/svp64-single/)
+* Test vectors for libopid and binutils