-This project is a collaboration between RED Semiconductor and LibreSOC to create binutil tools that support the development of Simple-V and SVP64 capabilities for the open-source RISC-V ISA. It will directly support the ISA Expansion project for which a separate grant application has been made, and will build on learnings from binutils developed for POWER ISA. The outcome of the project will be the completion of binutil tools capable of creating and managing binary program files, including handling object files, libraries, profile data, and assembly source code.
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-The completed tools will be made available to developers via LibreSOC's website and git repositories.
+This project is to enhance binutils tools to continue the autogenerated supportfor the
+RISC-V, Power and other ISAs, and to also support Simple-V Vectorisation capabilities.
+It will directly support the ISA Expansion project
+<https://libre-soc.org/nlnet_2023_simplev_riscv>
+for which a separate grant application has been made, and will build on learnings from
+binutils developed for POWER ISA and SVP64/Power. The outcome of the project will be the completion of binutil tools capable of creating and managing binary program files, including handling object files, libraries, profile data, and assembly source code, as well as
+providing a machine-readable database and associated library for other projects to
+manipulate supported Instruction sets.