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[libreriscv.git] / openpower / simple_v_spec.tex
diff --git a/openpower/simple_v_spec.tex b/openpower/simple_v_spec.tex
index f365cd76f03bad9a22168100a7a0e2e1f9b2dd00..b8b802f77ee32bf9efd74f147a9fb534a8992bf6 100644 (file)
--- a/openpower/simple_v_spec.tex
+++ b/openpower/simple_v_spec.tex
@@ -5,6 +5,11 @@
 \usepackage{sectsty}
 \usepackage{appendix}
 \usepackage{graphicx}
 \usepackage{sectsty}
 \usepackage{appendix}
 \usepackage{graphicx}
+\usepackage[firstpage]{draftwatermark}
+\usepackage[printonlyused,withpage]{acronym}
+\usepackage{float}
+\usepackage{url}
+\usepackage[useregional]{datetime2}
 \usepackage{anyfontsize}
 \usepackage{ifxetex,ifluatex}
 \usepackage{fixltx2e} % provides \textsubscript
 \usepackage{anyfontsize}
 \usepackage{ifxetex,ifluatex}
 \usepackage{fixltx2e} % provides \textsubscript
@@ -28,8 +33,10 @@
 }{}
 \PassOptionsToPackage{hyphens}{url} % url is loaded by hyperref
 \usepackage[unicode=true]{hyperref}
 }{}
 \PassOptionsToPackage{hyphens}{url} % url is loaded by hyperref
 \usepackage[unicode=true]{hyperref}
-\hypersetup{
-            pdfborder={0 0 0},
+\hypersetup{colorlinks=true,
+            linkcolor=blue,
+                filecolor=cyan,      
+                urlcolor=magenta,
             breaklinks=true}
 \usepackage[margin=0.9in]{geometry}
 \usepackage{color}
             breaklinks=true}
 \usepackage[margin=0.9in]{geometry}
 \usepackage{color}
@@ -71,6 +78,18 @@
 \newcommand{\ErrorTok}[1]{\textcolor[rgb]{1.00,0.00,0.00}{\textbf{#1}}}
 \newcommand{\NormalTok}[1]{#1}
 
 \newcommand{\ErrorTok}[1]{\textcolor[rgb]{1.00,0.00,0.00}{\textbf{#1}}}
 \newcommand{\NormalTok}[1]{#1}
 
+% these come from:
+% https://gist.github.com/bgeron/72ebbacf5930537022079d9953f15713
+\usepackage{newunicodechar}
+\newcommand\DeclareUnicodeInv[2]{\DeclareUnicodeCharacter{#2}{#1}}
+
+\DeclareUnicodeCharacter{03A0}{\ensuremath{\Pi}}
+\DeclareUnicodeCharacter{2208}{\ensuremath{\in}}
+\DeclareUnicodeCharacter{03C0}{\ensuremath{\pi}}
+\DeclareUnicodeCharacter{221A}{$\sqrt{}$}
+\DeclareUnicodeCharacter{221B}{$\sqrt[3]{}$}
+\DeclareUnicodeInv{\ensuremath{\mathbb{Z}}}{2124}
+
 % indent all verbatim
 \catcode`\@=11
 \let \saveverbatime \@xverbatim
 % indent all verbatim
 \catcode`\@=11
 \let \saveverbatime \@xverbatim
@@ -106,6 +125,8 @@ table}}{}
 \def\fps@figure{htbp}
 \makeatother
 
 \def\fps@figure{htbp}
 \makeatother
 
+% graphics path for primer
+\graphicspath{ {svp64-primer/img/} }
 
 \date{}
 
 
 \date{}
 
@@ -114,6 +135,8 @@ table}}{}
 \chapter*{Preamble}
 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 
 \chapter*{Preamble}
 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 
+\textbf{Last modified date: \today}
+
 This document is an auto-generated version of the Draft SVP64
 Specification available at
 
 This document is an auto-generated version of the Draft SVP64
 Specification available at
 
@@ -150,9 +173,58 @@ Simple-V is in DRAFT Status and will be submitted publicly
 Process. Funding from NLnet, through their Privacy and Enhanced Trust
 Programme, requires full transparency.
 
 Process. Funding from NLnet, through their Privacy and Enhanced Trust
 Programme, requires full transparency.
 
+As this document is under continuous rapid revision please check frequently
+at:
+
+\begin{verbatim}
+    https://ftp.libre-soc.org/simple_v_spec.pdf
+\end{verbatim}
+
+\subsection*{Contacts}
+For questions, comments, and clarification, please contact the following:
+\begin{itemize}
+    \itemsep -0.3em
+    \item Libre-SOC ISA Dev Mailing List - libre-soc-isa@lists.libre-soc.org
+    \item Luke Kenneth Casson Leighton - Libre-SOC team lead and Red 
+    Semiconductor Ltd Director - lkcl@lkcl.net
+    \item David Calderwood - Red Semiconductor Ltd Director - 
+    djac@calderwoodhan.com
+    \item Toshaan Bharvani - OpenPOWER Foundation Technical Chair, VanTosh 
+    Director - toshaan@vantosh.com
+    \item Konstantinos Margaritis -  Engineer and Founder of VectorCamp, writing optimised assembler for a number of SIMD/Vector ISAs  - konstantinos@vectorcamp.gr
+    \item Dmitry Selyutin - Libre-SOC engineer, working on binutils SVP64 assembler - ghostmansd@gmail.com
+    \item Jacob Lifshay - Libre-SOC engineer, CPU arch and verification - programmerjake@gmail.com
+    \item Cesar Strauss - Libre-SOC engineer, CPU arch and verification - cestrauss@gmail.com
+    \item Andrey Miroshnikov - Libre-SOC engineer, assisting with documentation - andrey@technepisteme.xyz
+\end{itemize}
+
+\newpage
+\subsection*{Executive Summary}
+\hypertarget{svux2fexecutive_summary}{}
+\input{tex_out/executive_summary.tex}
+ 
+\newpage
+\begin{landscape}
+\addcontentsline{toc}{chapter}{Comparison Table} \markboth{INTRODUCTION}{}
+\hypertarget{svux2fcomparison_table}{}
+{
+\fontsize{6}{8}\selectfont
+\input{tex_out/comparison_table.tex}
+}
+\end{landscape}
+
+\part{Scalable Vectors Primer}
+\input{svp64-primer/acronyms}
+%\chapter*{Executive Summary}
+\include{svp64-primer/summary}
+\bibliography{svp64-primer/references}
+\bibliographystyle{ieeetr}
+
 \tableofcontents
 
 \tableofcontents
 
-\part{Scalable Vectors}
+% Part II
+\part{Scalable Vectors for the Power ISA}
+
 
 \chapter{Fields and Forms}
 \hypertarget{svux2ffields}{}
 
 \chapter{Fields and Forms}
 \hypertarget{svux2ffields}{}
@@ -192,11 +264,17 @@ Programme, requires full transparency.
 
 \begin{appendices}
 \chapter{SVP64 Appendix}\hypertarget{svp64ux2fappendix}{}
 
 \begin{appendices}
 \chapter{SVP64 Appendix}\hypertarget{svp64ux2fappendix}{}
+\hypertarget{svux2fsvp64ux2fappendix}{}
 \input{tex_out/svp64_appendix.tex}
 \chapter{SVP64 Quirks}\hypertarget{svux2fsvp64_quirks}{}
 \input{tex_out/svp64_quirks.tex}
 \input{tex_out/svp64_appendix.tex}
 \chapter{SVP64 Quirks}\hypertarget{svux2fsvp64_quirks}{}
 \input{tex_out/svp64_quirks.tex}
+\chapter{REMAP algorithms}\hypertarget{svux2fremapux2fappendix}{}
+\input{tex_out/remap_appendix.tex}
 \chapter{Simple-V pseudocode}\hypertarget{svux2fpseudocode_simplev}{}
 \input{tex_out/pseudocode_simplev.tex}
 \chapter{Simple-V pseudocode}\hypertarget{svux2fpseudocode_simplev}{}
 \input{tex_out/pseudocode_simplev.tex}
+\chapter{Simple-V Analysis}\hypertarget{svux2fsv_analysis}{}
+\input{tex_out/sv_analysis.tex}
+
 \chapter{SVP64 Augmentation Table}\hypertarget{opcode_regs_deduped}{}
 \begin{landscape}
 {
 \chapter{SVP64 Augmentation Table}\hypertarget{opcode_regs_deduped}{}
 \begin{landscape}
 {
@@ -204,38 +282,97 @@ Programme, requires full transparency.
 \input{tex_out/opcode_regs_deduped.tex}
 }
 \end{landscape}
 \input{tex_out/opcode_regs_deduped.tex}
 }
 \end{landscape}
+
 \end{appendices}
 
 \end{appendices}
 
+% Part III
 \part{Scalar Instructions}
 
 \part{Scalar Instructions}
 
-\chapter{Vector Assist ops}\hypertarget{svux2fvector_ops}{}
+\chapter*{Preamble}{}
+
+As explained in the Simple-V introduction
+these are all intentionally and specifically Scalar instructions.
+Each section is free-standing, has no connection, dependence or
+relationship to any other section, including no direct critical dependence
+either way on Simple-V.
+They have with almost no exceptions been specifically crafted to
+have a justification for their inclusion in the Power ISA as Scalar
+instructions purely on their own merit.
+
+\begin{itemize}
+       \item The biginteger multiply-and-add instruction is similar
+       to Intel's mulx in that it produces a pair of results.
+       \item Javascript(tm) rounding is present in ARM as fjcvtzs
+       and would save an astounding 35 instructions with 5 branches.
+       \item Whilst there exist CR bit manipulation and copying
+       instructions there are no CR Field manipulation instructions,
+       putting pressure on GPRs if several CR fits need to be analysed.
+       \item one single instruction, bmask, is proposed that covers
+       the whole of x86 BMI1 and AMD TBM, combined, and provides more.
+\end{itemize}
+
+All of these have nothing to do with Simple-V at all: they make
+the Power ISA better at modern general-purpose compute, bringing
+it up-to-date.
+
+That said: by a wonderful coincidence, should they be included, then
+Simple-V's capabilities increase significantly. For example the CRweird
+instructions combined with the bitmanip instructions, alongside 
+Vectorised Rc=1 turn CR Fields into
+extremely powerful Predicate masks. bmask not only
+covers the BMI and TBM instructions of Intel and AMD it also
+includes the RVV set-before-first and set-after-first instructions.
+
+The clean and clear separation between Vectorisation Prefix and Scalar
+Suffix is what makes it possible for both Scalar-only and Scalable-Vectors
+to benefit.  It also makes proposal much easier, as there is no
+inter-dependence.
+
+It is however important to note that the rationale for these instructions
+comes from a more general-purpose modern computing paradigm that is
+outside of IBM's much more focussed and specialist traditional customer
+base. We deeply respect IBM's curator role of the Power ISA of the past 25
+years as much as we appreciate their courage in transferring that role
+to the OpenPOWER Foundation ISA Working Group.
+
+\chapter{SV Vector-assist Scalar ops}\hypertarget{svux2fvector_ops}{}
 \input{tex_out/vector_ops.tex}
 \chapter{CR Weird ops}\hypertarget{svux2fcr_int_predication}{}
 \input{tex_out/vector_ops.tex}
 \chapter{CR Weird ops}\hypertarget{svux2fcr_int_predication}{}
+\hypertarget{cr_int_predication}{}
 \input{tex_out/cr_int_predication.tex}
 \chapter{Bitmanip ops}\hypertarget{svux2fbitmanip}{}
 \input{tex_out/bitmanip.tex}
 \input{tex_out/cr_int_predication.tex}
 \chapter{Bitmanip ops}\hypertarget{svux2fbitmanip}{}
 \input{tex_out/bitmanip.tex}
-\chapter{FP/Integer conversion ops}\hypertarget{svux2fint_fp_mv}{}
+\chapter{FP/Int Conversion ops}\hypertarget{svux2fint_fp_mv}{}
 \input{tex_out/int_fp_mv.tex}
 \chapter{FP Class ops}\hypertarget{svux2ffclass}{}
 \input{tex_out/fclass.tex}
 \chapter{Audio and Video Opcodes}\hypertarget{svux2fav_opcodes}{}
 \input{tex_out/int_fp_mv.tex}
 \chapter{FP Class ops}\hypertarget{svux2ffclass}{}
 \input{tex_out/fclass.tex}
 \chapter{Audio and Video Opcodes}\hypertarget{svux2fav_opcodes}{}
+\hypertarget{av_opcodes}{}
 \input{tex_out/av_opcodes.tex}
 \chapter{Big Integer}\hypertarget{svux2fbiginteger}{}
 \input{tex_out/big_integer.tex}
 \input{tex_out/av_opcodes.tex}
 \chapter{Big Integer}\hypertarget{svux2fbiginteger}{}
 \input{tex_out/big_integer.tex}
+\chapter{Transcendentals}\hypertarget{transcendentals}{}
+\input{tex_out/transcendentals.tex}
+%\chapter{Acquire/Release Atomic Memory}\hypertarget{atomics}{}
+%\input{tex_out/atomics.tex}
 
 \begin{appendices}
 \chapter{Big Integer Analysis}\hypertarget{svux2fbigintegerux2fanalysis}{}
 \input{tex_out/big_integer_analysis.tex}
 \chapter{Bitmanip pseudocode}\hypertarget{svux2fpseudocode_bitmanip}{}
 \input{tex_out/pseudocode_bitmanip.tex}
 
 \begin{appendices}
 \chapter{Big Integer Analysis}\hypertarget{svux2fbigintegerux2fanalysis}{}
 \input{tex_out/big_integer_analysis.tex}
 \chapter{Bitmanip pseudocode}\hypertarget{svux2fpseudocode_bitmanip}{}
 \input{tex_out/pseudocode_bitmanip.tex}
-\chapter{Floating Point pseudocode}\hypertarget{svux2fpseudocode_svfparith}{}
+\chapter{Floating Point pseudocode}\hypertarget{isaux2fsvfparith}{}
 \input{tex_out/pseudocode_svfparith.tex}
 \chapter{Fixed Point pseudocode}
 \input{tex_out/pseudocode_svfparith.tex}
 \chapter{Fixed Point pseudocode}
-\hypertarget{svux2fpseudocode_svfixedarith}{}
+\hypertarget{isaux2fsvfixedarith}{}
 \input{tex_out/pseudocode_svfixedarith.tex}
 \end{appendices}
 
 \input{tex_out/pseudocode_svfixedarith.tex}
 \end{appendices}
 
+% Part IV
 \part{Scalar Power ISA pseudocode}
 \part{Scalar Power ISA pseudocode}
+\backmatter % temporary fix for too many appenfices
+%\setcounter{chapter}{0}
+%\renewcommand{\thechapter}{\Alph{chapter}}
 
 \chapter*{Preamble}
 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 
 \chapter*{Preamble}
 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
@@ -263,6 +400,7 @@ to extend to 128-bit in future (like RV128).
 \hypertarget{svux2fpseudocode_bcd}{}
 \input{tex_out/pseudocode_bcd.tex}
 \chapter{Branch pseudocode}
 \hypertarget{svux2fpseudocode_bcd}{}
 \input{tex_out/pseudocode_bcd.tex}
 \chapter{Branch pseudocode}
+\hypertarget{openpowerux2fisaux2fbranch}{}
 \hypertarget{svux2fpseudocode_branch}{}
 \input{tex_out/pseudocode_branch.tex}
 \chapter{Fixed Point Compare pseudocode}
 \hypertarget{svux2fpseudocode_branch}{}
 \input{tex_out/pseudocode_branch.tex}
 \chapter{Fixed Point Compare pseudocode}
http://libre-riscv.org ikiwiki