+ BF = BT[2:4] # select CR
+ bit = BT[0:1] # select bit of CR
+ result = n0|n1|n2|n3 if M else n0&n1&n2&n3
+ CR{BF}[bit] = result
+
+When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type operation that has
+5-bit Data-dependent and 5-bit Predicate-result capability
+(BFT is 5 bits)
+
+**Example Pseudo-ops:**
+
+ mtcri BF, mode mtcrweird BF, r0, 0, 0b1111.~mode
+ mtcrset BF, mask mtcrweird BF, r0, 1, mask.0b0000
+ mtcrclr BF, mask mtcrweird BF, r0, 1, mask.0b1111
+
+# Vectorised versions
+
+The name "weird" refers to a minor violation of SV rules when it comes to deriving the Vectorised versions of these instructions.
+
+Normally the progression of the SV for-loop would move on to the next register.
+Instead however in the scalar case these instructions **remain in the same register** and insert or transfer between **bits** of the scalar integer source or destination.
+
+Further useful violation of the normal SV Elwidth override rules allows
+for packing (or unpacking) of multiple CR test results into
+(or out of) an Integer Element. Note
+that the CR (source operand) elwidth field is utilised to determine the bit-
+packing size (1/2/4/8 with remaining bits within the Integer element
+set to zero) whilst the INT (dest operand) elwidth field still sets
+the Integer element size as usual (8/16/32/default)
+
+ crrweird: RT, BB, mask.mode
+
+ for i in range(VL):
+ if BB.isvec:
+ creg = CR{BB+i}
+ else:
+ creg = CR{BB}
+ n0 = mask[0] & (mode[0] == creg[0])
+ n1 = mask[1] & (mode[1] == creg[1])
+ n2 = mask[2] & (mode[2] == creg[2])
+ n3 = mask[3] & (mode[3] == creg[3])
+ # OR or AND to a single bit
+ result = n0|n1|n2|n3 if M else n0&n1&n2&n3
+ if RT.isvec:
+ # TODO: RT.elwidth override to be also added here
+ # note, yes, really, the CR's elwidth field determines
+ # the bit-packing into the INT!
+ if BB.elwidth == 0b00:
+ # pack 1 result into 64-bit registers
+ iregs[RT+i][0..62] = 0
+ iregs[RT+i][63] = result # sets LSB to result
+ if BB.elwidth == 0b01:
+ # pack 2 results sequentially into INT registers
+ iregs[RT+i//2][0..61] = 0
+ iregs[RT+i//2][63-(i%2)] = result
+ if BB.elwidth == 0b10:
+ # pack 4 results sequentially into INT registers
+ iregs[RT+i//4][0..59] = 0
+ iregs[RT+i//4][63-(i%4)] = result
+ if BB.elwidth == 0b11:
+ # pack 8 results sequentially into INT registers
+ iregs[RT+i//8][0..55] = 0
+ iregs[RT+i//8][63-(i%8)] = result
+ else:
+ iregs[RT][63-i] = result # results also in scalar INT
+
+Note that:
+
+* in the scalar case the CR-Vector assessment
+ is stored bit-wise starting at the LSB of the
+ destination scalar INT
+* in the INT-vector case the results are packed into LSBs
+ of the INT Elements, the packing arrangement depending on both
+ elwidth override settings.
+
+# v3.1 setbc instructions
+
+there are additional setb conditional instructions in v3.1 (p129)
+
+ RT = (CR[BI] == 1) ? 1 : 0
+
+which also negate that, and also return -1 / 0. these are similar to crweird but not the same purpose. most notable is that crweird acts on CR fields rather than the entire 32 bit CR.
+
+# Predication Examples
+
+Take the following example:
+
+ r10 = 0b00010
+ sv.mtcrweird/dm=r10/dz cr8.v, 0, 0b0011.0000
+
+Here, RA is zero, so the source input is zero. The destination
+is CR Field 8, and the destination predicate mask indicates
+to target the first two elements. Destination predicate zeroing is
+enabled, and the destination predicate is only set in the 2nd bit.
+mask is 0b0011, mode is all zeros.
+
+Let us first consider what should go into element 0 (CR Field 8):
+
+* The destination predicate bit is zero, and zeroing is enabled.
+* Therefore, what is in the source is irrelevant: the result must
+ be zero.
+* Therefore all four bits of CR Field 8 are therefore set to zero.