+
+Remember the following register files need to have for-loops, plus
+unit tests:
+
+* GPR
+* SPRs (yes, really: mtspr and mfspr are SV Context-extensible)
+* Condition Registers. see note below
+* FPR (if present)
+
+When Rc=1 is encountered in an SVP64 Context the destination is different (TODO) i.e. not CR0 or CR1. Implicit Rc=1 Condition Registers are still Vectorized but do **not** have EXTRA2/3 spec adjustments. The only part if the EXTRA2/3 spec that is observed and respected is whether the CR is Vectorized (isvec).
+
+## Increasing register file sizes
+
+TODO. INTs, FPs, CRs, these all increase to 128. Welcome To Vector ISAs.
+
+At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP scalar may also be adjusted.
+
+## Single and Twin Predication
+
+both CR and INT predication is needed, as well as zeroing in both.
+the order is best done as follows:
+
+* INT-based single
+* CR-based single
+* srcstep+dststep
+* INT-based twin
+* CR-based twin
+* Zeroing single
+* Zeroing twin
+
+Best done as a FSM that "advances" srcstep and dststep over the
+zeros in their respective predicate masks, *including* when the
+src and dest predicate mask is "All 1s".
+
+Bear in mind that srcstep+deststep are a form of back-to-back
+VGATHER+VSCATTER
+
+Watch out in zeroing! CR0 will *not* be set (itself) to zero:
+the CR0.eq flag will be set because the *result* is still tested.
+correction: CR0-and-any-other-Vector-of-CR-fields (Vector elements
+have their corresponding CR field, so the test of zero needs to
+be done for the associated *element* result, not jam absolutely
+every element vector test *into* CR0)
+
+Progress:
+
+* TestIssuer <https://bugs.libre-soc.org/show_bug.cgi?id=617>
+ and Zeroing <https://bugs.libre-soc.org/show_bug.cgi?id=636>
+* ISACaller <https://bugs.libre-soc.org/show_bug.cgi?id=618>
+* power-gem5: TODO
+* Microwatt: TODO
+
+## Element width overrides
+
+<https://bugs.libre-soc.org/show_bug.cgi?id=663>
+
+* Pseudocode: TODO
+* Simulator: TODO
+* TestIssuer: TODO
+* unit tests: TODO
+* power-gem5: TODO
+* cavatools: TODO
+
+## Reduce Mode
+
+TODO
+
+## Saturation Mode
+
+TODO
+
+## REMAP and Context Propagation
+
+* <https://libre-soc.org/openpower/sv/remap/>
+* <https://libre-soc.org/openpower/sv/propagation/>
+* <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/svp64.py;hb=HEAD>
+
+## Vectorized Branches
+
+TODO [[sv/branches]]
+
+## Vectorized LD/ST
+
+TODO [[sv/ldst]]