+* Java's
+ [FP -> Integer conversion](https://docs.oracle.com/javase/specs/jls/se16/html/jls-5.html#jls-5.1.3)
+* Rust's FP -> Integer conversion using the
+ [`as` operator](https://doc.rust-lang.org/reference/expressions/operator-expr.html#semantics)
+* LLVM's
+ [`llvm.fptosi.sat`](https://llvm.org/docs/LangRef.html#llvm-fptosi-sat-intrinsic) and
+ [`llvm.fptoui.sat`](https://llvm.org/docs/LangRef.html#llvm-fptoui-sat-intrinsic) intrinsics
+* SPIR-V's OpenCL dialect's
+ [`OpConvertFToU`](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#OpConvertFToU) and
+ [`OpConvertFToS`](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#OpConvertFToS)
+ instructions when decorated with
+ [the `SaturatedConversion` decorator](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#_a_id_decoration_a_decoration).
+* WebAssembly has also introduced
+ [trunc_sat_u](ttps://webassembly.github.io/spec/core/exec/numerics.html#op-trunc-sat-u) and
+ [trunc_sat_s](https://webassembly.github.io/spec/core/exec/numerics.html#op-trunc-sat-s)
+
+**JavaScript conversion**
+
+For the sake of simplicity, the FP -> Integer conversion semantics generalized from those used by JavaScripts's `ToInt32` abstract operation will be referred to as [JavaScript conversion semantics](#fp-to-int-javascript-conversion-semantics).
+
+This instruction is present in ARM assembler as FJCVTZS
+<https://developer.arm.com/documentation/dui0801/g/hko1477562192868>
+
+**Format**
+
+| 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 | Form |
+|--------|------|--------|-------|-------|----|------|
+| Major | RT | //Mode | FRA | XO | Rc |X-Form|
+
+**Rc=1 and OE=1**
+
+All of these insructions have an Rc=1 mode which sets CR0
+in the normal way for any instructions producing a GPR result.
+Additionally, when OE=1, if the numerical value of the FP number
+is not 100% accurately preserved (due to truncation or saturation
+and including when the FP number was NaN) then this is considered
+to be an integer Overflow condition, and CR0.SO, XER.SO and XER.OV
+are all set as normal for any GPR instructions that overflow.
+
+**Instructions**
+
+* `fcvttgw RT, FRA, Mode`
+ Convert from 64-bit float to 32-bit signed integer, writing the result
+ to the GPR `RT`. Converts using [mode `Mode`]. Similar to `fctiw` or `fctiwz`
+* `fcvttguw RT, FRA, Mode`
+ Convert from 64-bit float to 32-bit unsigned integer, writing the result
+ to the GPR `RT`. Converts using [mode `Mode`]. Similar to `fctiwu` or `fctiwuz`
+* `fcvttgd RT, FRA, Mode`
+ Convert from 64-bit float to 64-bit signed integer, writing the result
+ to the GPR `RT`. Converts using [mode `Mode`]. Similar to `fctid` or `fctidz`
+* `fcvttgud RT, FRA, Mode`
+ Convert from 64-bit float to 64-bit unsigned integer, writing the result
+ to the GPR `RT`. Converts using [mode `Mode`]. Similar to `fctidu` or `fctiduz`
+* `fcvtstgw RT, FRA, Mode`
+ Convert from 32-bit float to 32-bit signed integer, writing the result
+ to the GPR `RT`. Converts using [mode `Mode`]
+* `fcvtstguw RT, FRA, Mode`
+ Convert from 32-bit float to 32-bit unsigned integer, writing the result
+ to the GPR `RT`. Converts using [mode `Mode`]
+* `fcvtstgd RT, FRA, Mode`
+ Convert from 32-bit float to 64-bit signed integer, writing the result
+ to the GPR `RT`. Converts using [mode `Mode`]
+* `fcvtstgud RT, FRA, Mode`
+ Convert from 32-bit float to 64-bit unsigned integer, writing the result
+ to the GPR `RT`. Converts using [mode `Mode`]