+[[sv/remap]] allows up to four Vectors (all four arguments of `fma` for example)
+to be algorithmically arbitrarily remapped via 1D, 2D or 3D reshaping.
+The amount of information needed to do so is however quite large: consequently it is only practical to apply indirectly, via Context propagation.
+
+Vectors may be remapped such that Matrix multiply of any arbitrary size
+is performed in one Vectorised `fma` instruction as long as the total
+number of elements is less than 64 (maximum for VL).
+
+Additionally, in a fashion known as "Structure Packing" in NEON and RVV, it may be used to perform "zipping" and "unzipping" of
+elements in a regular fashion of any arbitrary size and depth: RGB
+or Audio channel data may be split into separate contiguous lanes of
+registers, for example.
+
+There are four possible Shapes. Unlike swizzle contexts this one requires
+he external remap Shape SPRs because the state information is too large
+to fit into the Context itself. Thus the Remap Context says which Shapes
+apply to which registers.
+
+The instruction format is the same as `RM` and thus uses 21 bits of
+immediate, 29 of which are dropped into the indexed Shift Register
+
+| 0.5| 6.8 | 9.10| 11.14 | 15.31| name |
+| -- | --- | --- | ---- | ---- | ------- |
+| OP | | MM | | | ?-Form |
+| OP | idx | 10 | brev | imm | Remap |
+| OP | idx | 11 | brev | imm | SUBVL Remap |
+
+SUBVL Remap applies the remapping even into the SUBVL Elements, for a total of `VL\*SUBVL` Elements. **swizzle may be applied on top as a second phase** after SUBVL Remap.
+
+brev field, which also applied down to SUBVL elements (not to the whole
+vec2/3/4, that would be handled by swizzle reordering):
+
+* bit 0 indicates that dest elements are byte-reversed
+* bit 1 indicates that src1 elements are byte-reversed
+* bit 2 indicates that src2 elements are byte-reversed
+* bit 3 indicates that src3 elements are byte-reversed
+
+Again it is the 24 bit `RM` that is interpreted differently:
+
+| 0 | 2 | 4 | 6 | 8 | 10.14 | 15..23 |
+| -- | -- | -- | -- | -- | ----- | ------ |
+|mi0 |mi1 |mi2 |mo0 |mo1 | en0-4 | rsv |
+
+si0-2 and so0-1 each select SVSHAPE0-3 to apply to a given register.
+si0-2 apply to RA, RB, RC respectively, as input registers, and
+likewise so0-1 apply to output registers. en0-4 indicate whether the
+SVSHAPE is actively applied or not.
+
+# setvl
+
+Fitting into 22 bits with 2 reserved and 2 for future
+expansion of SV Vector Length is a total of 24 bits
+which is exactly the same size as SVP64 RM