+```
+
+## Floating-Point Twin Multiply-Add FFT
+
+X-Form
+
+```
+ |0 |6 |11 |16 |21 |31 |
+ | PO | FRT | FRA | FRB | XO |Rc |
+```
+
+* ffmadd FRT,FRA,FRB (Rc=0)
+
+Pseudo-code:
+
+```
+ FRS <- FPMULADD64(FRT, FRA, FRB, -1, 1)
+ FRT <- FPMULADD64(FRT, FRA, FRB, 1, 1)
+```
+
+The two operations
+
+```
+ FRS <- -([(FRT) * (FRA)] - (FRB))
+ FRT <- [(FRT) * (FRA)] + (FRB)
+```
+
+are performed.
+
+The floating-point operand in register FRT is multiplied by the
+floating-point operand in register FRA. The float- ing-point operand in
+register FRB is added to this intermediate result, and the intermediate
+stored in FRS.
+
+Using the exact same values of FRT, FRT and FRB as used to create
+FRS, the floating-point operand in register FRT is multiplied by the
+floating-point operand in register FRA. The float- ing-point operand
+in register FRB is subtracted from this intermediate result, and the
+intermediate stored in FRT.
+
+FRT is created as if a `fmadd` operation had been performed. FRS is
+created as if a `fnmsub` operation had simultaneously been performed
+with the exact same register operands, in parallel, independently,
+at exactly the same time.
+
+FRT is a Read-Modify-Write operation.
+
+Note that if Rc=1 an Illegal Instruction is raised. Rc=1 is `RESERVED`
+
+Similar to `FRTp`, this instruction produces an implicit result, `FRS`,
+which under Scalar circumstances is defined as `FRT+1`. For SVP64 if
+`FRT` is a Vector, `FRS` begins immediately after the Vector `FRT`
+where the length of `FRT` is set by `SVSTATE.MAXVL` (Max Vector Length).
+
+Special Registers Altered:
+
+```
+ FPRF FR FI
+ FX OX UX XX
+ VXSNAN VXISI VXIMZ
+```
+
+
+## Floating-Point Add FFT/DCT [Single]
+
+A-Form
+
+```
+ |0 |6 |11 |16 |21 |26 |31 |
+ | PO | FRT | FRA | FRB | / | XO |Rc |
+```
+
+* ffadds FRT,FRA,FRB (Rc=0)
+
+Pseudo-code:
+
+```
+ FRT <- FPADD32(FRA, FRB)
+ FRS <- FPSUB32(FRB, FRA)
+```
+
+Special Registers Altered:
+
+```
+ FPRF FR FI
+ FX OX UX XX
+ VXSNAN VXISI
+```
+
+## Floating-Point Add FFT/DCT [Double]
+
+A-Form
+
+```
+ |0 |6 |11 |16 |21 |26 |31 |
+ | PO | FRT | FRA | FRB | / | XO |Rc |
+```
+
+* ffadd FRT,FRA,FRB (Rc=0)
+
+Pseudo-code:
+
+```
+ FRT <- FPADD64(FRA, FRB)
+ FRS <- FPSUB64(FRB, FRA)
+```
+
+Special Registers Altered:
+
+```
+ FPRF FR FI
+ FX OX UX XX
+ VXSNAN VXISI
+```
+
+## Floating-Point Subtract FFT/DCT [Single]
+
+A-Form
+
+```
+ |0 |6 |11 |16 |21 |26 |31 |
+ | PO | FRT | FRA | FRB | / | XO |Rc |
+```
+
+* ffsubs FRT,FRA,FRB (Rc=0)
+
+Pseudo-code:
+
+```
+ FRT <- FPSUB32(FRB, FRA)
+ FRS <- FPADD32(FRA, FRB)
+```
+
+Special Registers Altered:
+
+```
+ FPRF FR FI
+ FX OX UX XX
+ VXSNAN VXISI
+```
+
+## Floating-Point Subtract FFT/DCT [Double]
+
+A-Form
+
+```
+ |0 |6 |11 |16 |21 |26 |31 |
+ | PO | FRT | FRA | FRB | / | XO |Rc |
+```
+
+* ffsub FRT,FRA,FRB (Rc=0)
+
+Pseudo-code:
+
+```
+ FRT <- FPSUB64(FRB, FRA)
+ FRS <- FPADD64(FRA, FRB)
+```
+
+Special Registers Altered:
+
+```
+ FPRF FR FI
+ FX OX UX XX
+ VXSNAN VXISI