- prod1 <- MULS(RB, sum)[XLEN:(XLEN*2)-1]
- prod2 <- MULS(RB, diff)[XLEN:(XLEN*2)-1]
- res1 <- ROTL64(prod1, XLEN-n)
- res2 <- ROTL64(prod2, XLEN-n)
- m <- MASK(n, (XLEN-1))
- signbit1 <- res1[0]
- signbit2 <- res2[0]
- smask1 <- ([signbit1]*XLEN) & ¬m
- smask2 <- ([signbit2]*XLEN) & ¬m
- s64_1 <- [0]*(XLEN-1) || signbit1
- s64_2 <- [0]*(XLEN-1) || signbit2
- RT <- (res1 & m | smask1) + s64_1
- RS <- (res2 & m | smask2) + s64_2
-```
-
-Note that if Rc=1 an Illegal Instruction is raised.
-Rc=1 is `RESERVED`
-
-Similar to `RTp`, this instruction produces an implicit result,
-`RS`, which under Scalar circumstances is defined as `RT+1`.
-For SVP64 if `RT` is a Vector, `RS` begins immediately after the
-Vector `RT` where the length of `RT` is set by `SVSTATE.MAXVL`
-(Max Vector Length).
+ prod1 <- MULS(RB, sum)
+ prod1_lo <- prod1[XLEN:(XLEN*2)-1]
+ prod2 <- MULS(RB, diff)
+ prod2_lo <- prod2[XLEN:(XLEN*2)-1]
+ if n = 0 then
+ RT <- prod1_lo
+ RS <- prod2_lo
+ else
+ round <- [0]*XLEN
+ round[XLEN -n] <- 1
+ prod1_lo <- prod1_lo + round
+ prod2_lo <- prod2_lo + round
+ m <- MASK(n, (XLEN-1))
+ res1 <- ROTL64(prod1_lo, XLEN-n) & m
+ res2 <- ROTL64(prod2_lo, XLEN-n) & m
+ signbit1 <- prod1_lo[0]
+ signbit2 <- prod2_lo[0]
+ smask1 <- ([signbit1]*XLEN) & ¬m
+ smask2 <- ([signbit2]*XLEN) & ¬m
+ RT <- (res1 | smask1)
+ RS <- (res2 | smask2)
+```
+
+Note that if Rc=1 an Illegal Instruction is raised. Rc=1 is `RESERVED`
+
+Similar to `RTp`, this instruction produces an implicit result, `RS`,
+which under Scalar circumstances is defined as `RT+1`. For SVP64 if
+`RT` is a Vector, `RS` begins immediately after the Vector `RT` where
+the length of `RT` is set by `SVSTATE.MAXVL` (Max Vector Length).