+* needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
+
+# What we are *NOT* doing:
+
+* A processor that is fundamentally incompatible (noncompliant) with Power.
+ (**escape-sequencing requires and guarantees compatibility**).
+* Opcode 4 Signal Processing (SPE)
+* Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
+* Avoidable legacy opcodes
+
+# SimpleV
+
+see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
+SimpleV: a "hardware for-loop" which involves type-casting (both) the
+register files to "a sequence of elements". The **one** instruction
+(an unmodified **scalar** instruction) is interpreted as a *hardware
+for-loop* that issues **multiple** internal instructions with
+sequentially-incrementing register numbers.
+
+Thus it is completely unnecessary to add any vector opcodes - at all -
+saving hugely on both hardware and compiler development time when
+the concept is dropped on top of a pre-existing ISA.
+
+## Condition Registers
+
+Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1. When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
+
+## Carry
+
+SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
+
+# Integer Overflow / Saturate
+
+Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE). To be done instead as CSRs / vector-flags on *standard* arithmetic operations.