# * along with this program; if not, write to the Free Software
# * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
# */
# * along with this program; if not, write to the Free Software
# * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
# */
'K_MOD_EQ', 'K_AND_EQ', 'K_OR_EQ'),
('right', 'K_XOR_EQ', 'K_LS_EQ', 'K_RS_EQ', 'K_RSS_EQ'),
('right', '?', ':', 'K_inside'),
'K_MOD_EQ', 'K_AND_EQ', 'K_OR_EQ'),
('right', 'K_XOR_EQ', 'K_LS_EQ', 'K_RS_EQ', 'K_RSS_EQ'),
('right', '?', ':', 'K_inside'),
- ('left', 'K_LOR'),
- ('left', 'K_LAND'),
- ('left', '|'),
- ('left', '^', 'K_NXOR', 'K_NOR'),
- ('left', '&', 'K_NAND'),
- ('left', 'K_EQ', 'K_NE', 'K_CEQ', 'K_CNE', 'K_WEQ', 'K_WNE'),
- ('left', 'K_GE', 'K_LE', '<', '>'),
- ('left', 'K_LS', 'K_RS', 'K_RSS'),
- ('left', '+', '-'),
- ('left', '*', '/', '%'),
- ('left', 'K_POW'),
- ('left', 'UNARY_PREC'),
- ('nonassoc', 'less_than_K_else'),
- ('nonassoc', 'K_else'),
- ('nonassoc', '('),
- ('nonassoc', 'K_exclude'),
- ('nonassoc', 'no_timeunits_declaration'),
- ('nonassoc', 'one_timeunits_declaration'),
+ ('left', 'K_LOR'),
+ ('left', 'K_LAND'),
+ ('left', '|'),
+ ('left', '^', 'K_NXOR', 'K_NOR'),
+ ('left', '&', 'K_NAND'),
+ ('left', 'K_EQ', 'K_NE', 'K_CEQ', 'K_CNE', 'K_WEQ', 'K_WNE'),
+ ('left', 'K_GE', 'K_LE', '<', '>'),
+ ('left', 'K_LS', 'K_RS', 'K_RSS'),
+ ('left', '+', '-'),
+ ('left', '*', '/', '%'),
+ ('left', 'K_POW'),
+ ('left', 'UNARY_PREC'),
+ ('nonassoc', 'less_than_K_else'),
+ ('nonassoc', 'K_else'),
+ ('nonassoc', '('),
+ ('nonassoc', 'K_exclude'),
+ ('nonassoc', 'no_timeunits_declaration'),
+ ('nonassoc', 'one_timeunits_declaration'),
+
+
+IVL_VT_NO_TYPE = 'VT_NO_TYPE'
+IVL_VT_BOOL = 'VT_BOOL'
+IVL_VT_LOGIC = 'VT_LOGIC'
+"""
+ IVL_VT_VOID = 0, /* Not used */
+ IVL_VT_NO_TYPE = 1, /* Place holder for missing/unknown type. */
+ IVL_VT_REAL = 2,
+ IVL_VT_BOOL = 3,
+ IVL_VT_LOGIC = 4,
+ IVL_VT_STRING = 5,
+ IVL_VT_DARRAY = 6, /* Array (esp. dynamic array) */
+ IVL_VT_CLASS = 7, /* SystemVerilog class instances */
+ IVL_VT_QUEUE = 8, /* SystemVerilog queue instances */
+ IVL_VT_VECTOR = IVL_VT_LOGIC /* For compatibility */
+"""
+
+NN_NONE = 'NONE'
+NN_IMPLICIT = 'IMPLICIT'
+NN_IMPLICIT_REG = 'IMPLICIT_REG'
+NN_INTEGER = 'INTEGER'
+NN_WIRE = 'WIRE'
+NN_TRI = 'TRI'
+NN_TRI1 = 'TRI1'
+NN_SUPPLY0 = 'SUPPLY0'
+NN_SUPPLY1 = 'SUPPLY1'
+NN_WAND = 'WAND'
+NN_TRIAND = 'TRIAND'
+NN_TRI0 = 'TRI0'
+NN_WOR = 'WOR'
+NN_TRIOR = 'TRIOR'
+NN_REG = 'REG'
+NN_UNRESOLVED_WIRE = 'UNRESOLVED_WIRE'
+
+NP_NOT_A_PORT = 'NOT_A_PORT'
+NP_PIMPLICIT = 'PIMPLICIT'
+NP_PINPUT = 'PINPUT'
+NP_POUTPUT = 'POUTPUT'
+NP_PINOUT = 'PINOUT'
+NP_PREF = 'PREF'
+
+
+
+
+class DataType:
+ def __init__(self, typ, signed):
+ self.typ = typ
+ self.signed = signed
+
# { list<pform_range_t>*pd = make_range_from_width(64);
# vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, false, pd);
# tmp->reg_flag = !gn_system_verilog();
# { list<pform_range_t>*pd = make_range_from_width(64);
# vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, false, pd);
# tmp->reg_flag = !gn_system_verilog();
# pform_pop_scope();
# vector<Statement*>tmp_for_list (1);
# tmp_for_list[0] = tmp_for;
# PBlock*tmp_blk = current_block_stack.top();
# current_block_stack.pop();
# tmp_blk->set_statement(tmp_for_list);
# pform_pop_scope();
# vector<Statement*>tmp_for_list (1);
# tmp_for_list[0] = tmp_for;
# PBlock*tmp_blk = current_block_stack.top();
# current_block_stack.pop();
# tmp_blk->set_statement(tmp_for_list);
# pform_pop_scope();
# vector<Statement*>tmp_for_list(1);
# tmp_for_list[0] = tmp_for;
# PBlock*tmp_blk = current_block_stack.top();
# current_block_stack.pop();
# tmp_blk->set_statement(tmp_for_list);
# pform_pop_scope();
# vector<Statement*>tmp_for_list(1);
# tmp_for_list[0] = tmp_for;
# PBlock*tmp_blk = current_block_stack.top();
# current_block_stack.pop();
# tmp_blk->set_statement(tmp_for_list);
# { if (last_modport_port.type != MP_TF)
# yyerror(@3, "error: task/function declaration not allowed here.");
# }
()
def p_modport_ports_list_5(p):
'''modport_ports_list : modport_ports_list ',' IDENTIFIER '''
# { if (last_modport_port.type != MP_TF)
# yyerror(@3, "error: task/function declaration not allowed here.");
# }
()
def p_modport_ports_list_5(p):
'''modport_ports_list : modport_ports_list ',' IDENTIFIER '''
- print(p)
- # { $$ = pform_verinum_with_size($1,$2, @2.text, @2.first_line);
+ if(parse_debug): print('number_3', list(p))
+ num = Leaf(token.NUMBER, "%s:%s" % (p[1], p[2]))
+ p[0] = num
+ # { p[0] = pform_verinum_with_size(p[1],p[2], @2.text, @2.first_line);
# { list<pform_range_t>*pd = make_range_from_width(integer_width);
# vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, true, pd);
# tmp->reg_flag = true;
# tmp->integer_flag = true;
# { list<pform_range_t>*pd = make_range_from_width(integer_width);
# vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, true, pd);
# tmp->reg_flag = true;
# tmp->integer_flag = true;
# { list<pform_range_t>*pd = make_range_from_width(64);
# vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, false, pd);
# tmp->reg_flag = !gn_system_verilog();
# { list<pform_range_t>*pd = make_range_from_width(64);
# vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, false, pd);
# tmp->reg_flag = !gn_system_verilog();
# { // Last step: check any closing name. This is done late so
# // that the parser can look ahead to detect the present
# // endlabel_opt but still have the pform_endmodule() called
# // early enough that the lexor can know we are outside the
# // module.
# { // Last step: check any closing name. This is done late so
# // that the parser can look ahead to detect the present
# // endlabel_opt but still have the pform_endmodule() called
# // early enough that the lexor can know we are outside the
# // module.
# { // Last step: check any closing name. This is done late so
# // that the parser can look ahead to detect the present
# // endlabel_opt but still have the pform_endmodule() called
# // early enough that the lexor can know we are outside the
# // module.
# { // Last step: check any closing name. This is done late so
# // that the parser can look ahead to detect the present
# // endlabel_opt but still have the pform_endmodule() called
# // early enough that the lexor can know we are outside the
# // module.
# { // Last step: check any closing name. This is done late so
# // that the parser can look ahead to detect the present
# // endlabel_opt but still have the pform_endmodule() called
# // early enough that the lexor can know we are outside the
# // module.
# { // Last step: check any closing name. This is done late so
# // that the parser can look ahead to detect the present
# // endlabel_opt but still have the pform_endmodule() called
# // early enough that the lexor can know we are outside the
# // module.
# { // Last step: check any closing name. This is done late so
# // that the parser can look ahead to detect the present
# // endlabel_opt but still have the pform_endmodule() called
# // early enough that the lexor can know we are outside the
# // module.
# { // Last step: check any closing name. This is done late so
# // that the parser can look ahead to detect the present
# // endlabel_opt but still have the pform_endmodule() called
# // early enough that the lexor can know we are outside the
# // module.
- # vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1, IVL_VT_LOGIC, true,
- # range_stub, $3, true);
- # $$ = tmp;
+ # vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, p[1], IVL_VT_LOGIC, true,
+ # range_stub, p[3], true);
+ # p[0] = tmp;
# yyerror(@4, "internal error: How can there be an unpacked range here?\n");
# }
# tmp = pform_make_task_ports(@3, use_port_type,
# port_declaration_context.data_type,
# ilist);
# yyerror(@4, "internal error: How can there be an unpacked range here?\n");
# }
# tmp = pform_make_task_ports(@3, use_port_type,
# port_declaration_context.data_type,
# ilist);
# } else {
# // Otherwise, the decorations for this identifier
# // indicate the type. Save the type for any right
# // context that may come later.
# port_declaration_context.port_type = use_port_type;
# } else {
# // Otherwise, the decorations for this identifier
# // indicate the type. Save the type for any right
# // context that may come later.
# port_declaration_context.port_type = use_port_type;
- # if ($1 && $3) {
- # size_t s1 = $1->size();
- # tmp = $1;
- # tmp->resize(tmp->size()+$3->size());
- # for (size_t idx = 0 ; idx < $3->size() ; idx += 1)
- # tmp->at(s1+idx) = $3->at(idx);
- # delete $3;
- # } else if ($1) {
- # tmp = $1;
+ # if (p[1] && p[3]) {
+ # size_t s1 = p[1]->size();
+ # tmp = p[1];
+ # tmp->resize(tmp->size()+p[3]->size());
+ # for (size_t idx = 0 ; idx < p[3]->size() ; idx += 1)
+ # tmp->at(s1+idx) = p[3]->at(idx);
+ # delete p[3];
+ # } else if (p[1]) {
+ # tmp = p[1];
# enum_type->base_type = IVL_VT_BOOL;
# enum_type->signed_flag = true;
# enum_type->integer_flag = false;
# enum_type->range.reset(make_range_from_width(32));
# enum_type->base_type = IVL_VT_BOOL;
# enum_type->signed_flag = true;
# enum_type->integer_flag = false;
# enum_type->range.reset(make_range_from_width(32));
- print(p)
- # { perm_string name = lex_strings.make($1);
- # long count = check_enum_seq_value(@1, $3, false);
- # delete[]$1;
- # $$ = make_named_numbers(name, 0, count-1);
- # delete $3;
+ if(parse_debug): print('enum_name_2', list(p))
+ # { perm_string name = lex_strings.make(p[1]);
+ # long count = check_enum_seq_value(@1, p[3], false);
+ # delete[]p[1];
+ # p[0] = make_named_numbers(name, 0, count-1);
+ # delete p[3];
- print(p)
- # { perm_string name = lex_strings.make($1);
- # $$ = make_named_numbers(name, check_enum_seq_value(@1, $3, true),
- # check_enum_seq_value(@1, $5, true));
- # delete[]$1;
- # delete $3;
- # delete $5;
+ if(parse_debug): print('enum_name_3', list(p))
+ # { perm_string name = lex_strings.make(p[1]);
+ # p[0] = make_named_numbers(name, check_enum_seq_value(@1, p[3], true),
+ # check_enum_seq_value(@1, p[5], true));
+ # delete[]p[1];
+ # delete p[3];
+ # delete p[5];
- print(p)
- # { perm_string name = lex_strings.make($1);
- # long count = check_enum_seq_value(@1, $3, false);
- # $$ = make_named_numbers(name, 0, count-1, $6);
- # delete[]$1;
- # delete $3;
+ if(parse_debug): print('enum_name_5', list(p))
+ # { perm_string name = lex_strings.make(p[1]);
+ # long count = check_enum_seq_value(@1, p[3], false);
+ # p[0] = make_named_numbers(name, 0, count-1, p[6]);
+ # delete[]p[1];
+ # delete p[3];
- print(p)
- # { perm_string name = lex_strings.make($1);
- # $$ = make_named_numbers(name, check_enum_seq_value(@1, $3, true),
- # check_enum_seq_value(@1, $5, true), $8);
- # delete[]$1;
- # delete $3;
- # delete $5;
+ if(parse_debug): print('enum_name_6', list(p))
+ # { perm_string name = lex_strings.make(p[1]);
+ # p[0] = make_named_numbers(name, check_enum_seq_value(@1, p[3], true),
+ # check_enum_seq_value(@1, p[5], true), p[8]);
+ # delete[]p[1];
+ # delete p[3];
+ # delete p[5];
# port_declaration_context.port_type,
# port_declaration_context.port_net_type,
# port_declaration_context.data_type, 0);
# port_declaration_context.port_type,
# port_declaration_context.port_net_type,
# port_declaration_context.data_type, 0);
# ptmp = pform_module_port_reference(name, @2.text,
# @2.first_line);
# real_type_t*real_type = new real_type_t(real_type_t::REAL);
# FILE_NAME(real_type, @3);
# pform_module_define_port(@2, name, NetNet::PINPUT,
# ptmp = pform_module_port_reference(name, @2.text,
# @2.first_line);
# real_type_t*real_type = new real_type_t(real_type_t::REAL);
# FILE_NAME(real_type, @3);
# pform_module_define_port(@2, name, NetNet::PINPUT,
# ptmp = pform_module_port_reference(name, @2.text,
# @2.first_line);
# real_type_t*real_type = new real_type_t(real_type_t::REAL);
# FILE_NAME(real_type, @3);
# pform_module_define_port(@2, name, NetNet::PINOUT,
# ptmp = pform_module_port_reference(name, @2.text,
# @2.first_line);
# real_type_t*real_type = new real_type_t(real_type_t::REAL);
# FILE_NAME(real_type, @3);
# pform_module_define_port(@2, name, NetNet::PINOUT,
- # perm_string name = lex_strings.make($5);
- # data_type_t*use_dtype = $4;
- # if ($6) use_dtype = new uarray_type_t(use_dtype, $6);
- # NetNet::Type use_type = $3;
+ # perm_string name = lex_strings.make(p[5]);
+ # data_type_t*use_dtype = p[4];
+ # if (p[6]) use_dtype = new uarray_type_t(use_dtype, p[6]);
+ # NetNet::Type use_type = p[3];
# ptmp = pform_module_port_reference(name, @2.text,
# @2.first_line);
# real_type_t*real_type = new real_type_t(real_type_t::REAL);
# FILE_NAME(real_type, @3);
# pform_module_define_port(@2, name, NetNet::POUTPUT,
# ptmp = pform_module_port_reference(name, @2.text,
# @2.first_line);
# real_type_t*real_type = new real_type_t(real_type_t::REAL);
# FILE_NAME(real_type, @3);
# pform_module_define_port(@2, name, NetNet::POUTPUT,
- print(p)
- # { // Last step: check any closing name. This is done late so
- # // that the parser can look ahead to detect the present
- # // endlabel_opt but still have the pform_endmodule() called
- # // early enough that the lexor can know we are outside the
- # // module.
- # if ($17) {
- # if (strcmp($4,$17) != 0) {
- # switch ($2) {
- # case K_module:
- # yyerror(@17, "error: End label doesn't match "
- # "module name.");
- # break;
- # case K_program:
- # yyerror(@17, "error: End label doesn't match "
- # "program name.");
- # break;
- # case K_interface:
- # yyerror(@17, "error: End label doesn't match "
- # "interface name.");
- # break;
- # default:
- # break;
- # }
- # }
- # if (($2 == K_module) && (! gn_system_verilog())) {
- # yyerror(@8, "error: Module end labels require "
- # "SystemVerilog.");
- # }
- # delete[]$17;
- # }
- # delete[]$4;
- # }
+ if(parse_debug>2): print('module_1', list(p))
+ clsdecl = absyn.module_1(p)
+ p[0] = clsdecl
# if (dtype->implicit_flag)
# use_type = NetNet::NONE;
# else if (dtype->reg_flag)
# use_type = NetNet::REG;
# else
# use_type = NetNet::IMPLICIT_REG;
# if (dtype->implicit_flag)
# use_type = NetNet::NONE;
# else if (dtype->reg_flag)
# use_type = NetNet::REG;
# else
# use_type = NetNet::IMPLICIT_REG;
- print(p)
- # { pform_makegates(@1, PGBuiltin::PULLUP, pull_strength, 0, $2, 0); }
+ if(parse_debug): print('module_item_27', list(p))
+ # { pform_makegates(@1, PGBuiltin::PULLUP, pull_strength, 0, p[2], 0); }
- print(p)
- # { pform_makegates(@1, PGBuiltin::PULLDOWN, pull_strength, 0, $2, 0); }
+ if(parse_debug): print('module_item_28', list(p))
+ # { pform_makegates(@1, PGBuiltin::PULLDOWN, pull_strength, 0, p[2], 0); }
- print(p)
- # { perm_string tmp1 = lex_strings.make($2);
- # pform_make_modgates(@2, tmp1, $3, $4, $1);
- # delete[]$2;
+ if(parse_debug): print('module_item_35', list(p))
+ # { perm_string tmp1 = lex_strings.make(p[2]);
+ # pform_make_modgates(@2, tmp1, p[3], p[4], p[1]);
+ # delete[]p[2];
- print(p)
- # { perm_string tmp3 = lex_strings.make($3);
- # perm_string tmp5 = lex_strings.make($5);
- # pform_set_attrib(tmp3, tmp5, $7);
- # delete[] $3;
- # delete[] $5;
+ if(parse_debug): print('module_item_65', list(p))
+ # { perm_string tmp3 = lex_strings.make(p[3]);
+ # perm_string tmp5 = lex_strings.make(p[5]);
+ # pform_set_attrib(tmp3, tmp5, p[7]);
+ # delete[] p[3];
+ # delete[] p[5];
- print(p)
- # { PExpr*tmp = $3;
- # pform_set_parameter(@1, lex_strings.make($1), param_active_type,
- # param_active_signed, param_active_range, tmp, $4);
- # delete[]$1;
+ if(parse_debug): print('parameter_assign_1', list(p))
+ tpname = Node(syms.tname, [Leaf(token.NAME, p[1])])
+ expr = Node(syms.tfpdef, [tpname, Leaf(token.EQUAL, p[2]), p[3] ])
+ p[0] = expr
+ # { PExpr*tmp = p[3];
+ # pform_set_parameter(@1, lex_strings.make(p[1]), param_active_type,
+ # param_active_signed, param_active_range, tmp, p[4]);
+ # delete[]p[1];
# pform_makewire(@1, name, NetNet::REG,
# NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
# pform_makewire(@1, name, NetNet::REG,
# NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
# { if (pform_peek_scope()->var_init_needs_explicit_lifetime()
# && (var_lifetime == LexicalScope::INHERITED)) {
# cerr << @3 << ": warning: Static variable initialization requires "
# "explicit lifetime in this context." << endl;
# warn_count += 1;
# }
# { if (pform_peek_scope()->var_init_needs_explicit_lifetime()
# && (var_lifetime == LexicalScope::INHERITED)) {
# cerr << @3 << ": warning: Static variable initialization requires "
# "explicit lifetime in this context." << endl;
# warn_count += 1;
# }
# pform_makewire(@1, name, NetNet::REG,
# NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
# pform_makewire(@1, name, NetNet::REG,
# NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
# pform_makewire(@1, name, NetNet::IMPLICIT,
# NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
# pform_makewire(@1, name, NetNet::IMPLICIT,
# NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
- print(p)
- # { int edge_flag = $2? 1 : -1;
- # $$ = pform_make_specify_edge_path(@1, edge_flag, $3, $4, false, $7, $9);}
+ if(parse_debug): print('specify_edge_path_2', list(p))
+ # { int edge_flag = p[2]? 1 : -1;
+ # p[0] = pform_make_specify_edge_path(@1, edge_flag, p[3], p[4], false, p[7], p[9]);}
- print(p)
- # { int edge_flag = $2? 1 : -1;
- # $$ = pform_make_specify_edge_path(@1, edge_flag, $3, $4, true, $7, $9); }
+ if(parse_debug): print('specify_edge_path_4', list(p))
+ # { int edge_flag = p[2]? 1 : -1;
+ # p[0] = pform_make_specify_edge_path(@1, edge_flag, p[3], p[4], true, p[7], p[9]); }
# { if (gn_specify_blocks_flag) {
# yywarn(@4, "Bit selects are not currently supported "
# "in path declarations. The declaration "
# "will be applied to the whole vector.");
# }
# list<perm_string>*tmp = new list<perm_string>;
# { if (gn_specify_blocks_flag) {
# yywarn(@4, "Bit selects are not currently supported "
# "in path declarations. The declaration "
# "will be applied to the whole vector.");
# }
# list<perm_string>*tmp = new list<perm_string>;
# { if (gn_specify_blocks_flag) {
# yywarn(@4, "Part selects are not currently supported "
# "in path declarations. The declaration "
# "will be applied to the whole vector.");
# }
# list<perm_string>*tmp = new list<perm_string>;
# { if (gn_specify_blocks_flag) {
# yywarn(@4, "Part selects are not currently supported "
# "in path declarations. The declaration "
# "will be applied to the whole vector.");
# }
# list<perm_string>*tmp = new list<perm_string>;
# { if (gn_specify_blocks_flag) {
# yywarn(@4, "Bit selects are not currently supported "
# "in path declarations. The declaration "
# "will be applied to the whole vector.");
# }
# { if (gn_specify_blocks_flag) {
# yywarn(@4, "Bit selects are not currently supported "
# "in path declarations. The declaration "
# "will be applied to the whole vector.");
# }
# { if (gn_specify_blocks_flag) {
# yywarn(@4, "Part selects are not currently supported "
# "in path declarations. The declaration "
# "will be applied to the whole vector.");
# }
# { if (gn_specify_blocks_flag) {
# yywarn(@4, "Part selects are not currently supported "
# "in path declarations. The declaration "
# "will be applied to the whole vector.");
# }
- print(p)
- # { PExpr*del = $1->front();
- # assert($1->size() == 1);
- # delete $1;
- # PDelayStatement*tmp = new PDelayStatement(del, $2);
+ if(parse_debug): print('statement_item_29', list(p))
+ # { PExpr*del = p[1]->front();
+ # assert(p[1]->size() == 1);
+ # delete p[1];
+ # PDelayStatement*tmp = new PDelayStatement(del, p[2]);
- print(p)
- # { PAssign*tmp = new PAssign($1,$3);
+ if(parse_debug): print('statement_item33', list(p))
+ if p[3]:
+ expr = Node(syms.expr_stmt, [p[1], Leaf(token.EQUAL, p[2]), p[3] ])
+ if(parse_debug): print ("expr TODO", repr(expr))
+ else:
+ expr = Node(syms.expr_stmt, [p[1], Leaf(token.EQUAL, p[2]), ])
+ if(parse_debug): print ("expr", repr(expr))
+ if(parse_debug): print ("expr (python):'%s'" % expr)
+ p[0] = expr
+ # { PAssign*tmp = new PAssign(p[1],p[3]);
- print(p)
- # { PExpr*del = $3->front(); $3->pop_front();
- # assert($3->empty());
- # PAssign*tmp = new PAssign($1,del,$4);
+ if(parse_debug): print('statement_item_37', list(p))
+ # { PExpr*del = p[3]->front(); p[3]->pop_front();
+ # assert(p[3]->empty());
+ # PAssign*tmp = new PAssign(p[1],del,p[4]);
- print(p)
- # { PExpr*del = $3->front(); $3->pop_front();
- # assert($3->empty());
- # PAssignNB*tmp = new PAssignNB($1,del,$4);
+ if(parse_debug): print('statement_item_38', list(p))
+ # { PExpr*del = p[3]->front(); p[3]->pop_front();
+ # assert(p[3]->empty());
+ # PAssignNB*tmp = new PAssignNB(p[1],del,p[4]);
- print(p)
- # { vector<PWire*>*tmp = $1;
- # size_t s1 = $1->size();
- # tmp->resize(s1+$2->size());
- # for (size_t idx = 0 ; idx < $2->size() ; idx += 1)
- # tmp->at(s1+idx) = $2->at(idx);
- # $$ = tmp;
- # delete $2;
+ if(parse_debug): print('udp_port_decls_2', list(p))
+ # { vector<PWire*>*tmp = p[1];
+ # size_t s1 = p[1]->size();
+ # tmp->resize(s1+p[2]->size());
+ # for (size_t idx = 0 ; idx < p[2]->size() ; idx += 1)
+ # tmp->at(s1+idx) = p[2]->at(idx);
+ # p[0] = tmp;
+ # delete p[2];
- print(p)
- # { perm_string tmp2 = lex_strings.make($2);
- # pform_make_udp(tmp2, $4, $7, $9, $8,
+ if(parse_debug): print('udp_primitive_1', list(p))
+ # { perm_string tmp2 = lex_strings.make(p[2]);
+ # pform_make_udp(tmp2, p[4], p[7], p[9], p[8],
- print(p)
- # { perm_string tmp2 = lex_strings.make($2);
- # perm_string tmp6 = lex_strings.make($6);
- # pform_make_udp(tmp2, $5, tmp6, $7, $9, $12,
+ if(parse_debug): print('udp_primitive_2', list(p))
+ # { perm_string tmp2 = lex_strings.make(p[2]);
+ # perm_string tmp6 = lex_strings.make(p[6]);
+ # pform_make_udp(tmp2, p[5], tmp6, p[7], p[9], p[12],