- RTLIL::SigSpec mask_en_naive(RTLIL::SigSpec do_mask, RTLIL::SigSpec bits, RTLIL::SigSpec mask_bits)
- {
- // this is the naive version of the function that does not care about grouping the EN bits.
-
- RTLIL::SigSpec inv_mask_bits = module->Not(NEW_ID, mask_bits);
- RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.size()), inv_mask_bits, do_mask);
- RTLIL::SigSpec result = module->And(NEW_ID, inv_mask_bits_filtered, bits);
- return result;
- }
-
- RTLIL::SigSpec mask_en_grouped(RTLIL::SigSpec do_mask, RTLIL::SigSpec bits, RTLIL::SigSpec mask_bits)
- {
- // this version of the function preserves the bit grouping in the EN bits.
-
- std::vector<RTLIL::SigBit> v_bits = bits;
- std::vector<RTLIL::SigBit> v_mask_bits = mask_bits;
-
- std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, std::pair<int, std::vector<int>>> groups;
- RTLIL::SigSpec grouped_bits, grouped_mask_bits;
-
- for (int i = 0; i < bits.size(); i++) {
- std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
- if (groups.count(key) == 0) {
- groups[key].first = grouped_bits.size();
- grouped_bits.append_bit(v_bits[i]);
- grouped_mask_bits.append_bit(v_mask_bits[i]);
- }
- groups[key].second.push_back(i);
- }
-
- std::vector<RTLIL::SigBit> grouped_result = mask_en_naive(do_mask, grouped_bits, grouped_mask_bits);
- RTLIL::SigSpec result;
-
- for (int i = 0; i < bits.size(); i++) {
- std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
- result.append_bit(grouped_result.at(groups.at(key).first));
- }
-
- return result;
- }
-
- void merge_en_data(RTLIL::SigSpec &merged_en, RTLIL::SigSpec &merged_data, RTLIL::SigSpec next_en, RTLIL::SigSpec next_data)
- {
- std::vector<RTLIL::SigBit> v_old_en = merged_en;
- std::vector<RTLIL::SigBit> v_next_en = next_en;
-
- // The new merged_en signal is just the old merged_en signal and next_en OR'ed together.
- // But of course we need to preserve the bit grouping..
-
- std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups;
- std::vector<RTLIL::SigBit> grouped_old_en, grouped_next_en;
- RTLIL::SigSpec new_merged_en;
-
- for (int i = 0; i < int(v_old_en.size()); i++) {
- std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_old_en[i], v_next_en[i]);
- if (groups.count(key) == 0) {
- groups[key] = grouped_old_en.size();
- grouped_old_en.push_back(key.first);
- grouped_next_en.push_back(key.second);
- }
- }
-
- std::vector<RTLIL::SigBit> grouped_new_en = module->Or(NEW_ID, grouped_old_en, grouped_next_en);
-
- for (int i = 0; i < int(v_old_en.size()); i++) {
- std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_old_en[i], v_next_en[i]);
- new_merged_en.append_bit(grouped_new_en.at(groups.at(key)));
- }
-
- // Create the new merged_data signal.
-
- RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.size());
-
- RTLIL::SigSpec old_data_set = module->And(NEW_ID, merged_en, merged_data);
- RTLIL::SigSpec old_data_unset = module->And(NEW_ID, merged_en, module->Not(NEW_ID, merged_data));
-
- RTLIL::SigSpec new_data_set = module->And(NEW_ID, next_en, next_data);
- RTLIL::SigSpec new_data_unset = module->And(NEW_ID, next_en, module->Not(NEW_ID, next_data));
-
- new_merged_data = module->Or(NEW_ID, new_merged_data, old_data_set);
- new_merged_data = module->And(NEW_ID, new_merged_data, module->Not(NEW_ID, old_data_unset));
-
- new_merged_data = module->Or(NEW_ID, new_merged_data, new_data_set);
- new_merged_data = module->And(NEW_ID, new_merged_data, module->Not(NEW_ID, new_data_unset));
-
- // Update merged_* signals
-
- merged_en = new_merged_en;
- merged_data = new_merged_data;
- }
-
- void consolidate_wr_by_addr(std::string memid, std::vector<RTLIL::Cell*> &wr_ports)