- // Fully pad all unused input connections of this box cell with S0
- // Fully pad all undriven output connections of this box cell with anonymous wires
- for (const auto &port_name : box_module->ports) {
- RTLIL::Wire* w = box_module->wire(port_name);
- log_assert(w);
- auto it = cell->connections_.find(port_name);
- if (w->port_input) {
- RTLIL::SigSpec rhs;
- if (it != cell->connections_.end()) {
- if (GetSize(it->second) < GetSize(w))
- it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
- rhs = it->second;
- }
- else {
- rhs = RTLIL::SigSpec(State::S0, GetSize(w));
- cell->setPort(port_name, rhs);
- }
- }
- if (w->port_output) {
- RTLIL::SigSpec rhs;
- auto it = cell->connections_.find(w->name);
- if (it != cell->connections_.end()) {
- if (GetSize(it->second) < GetSize(w))
- it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
- rhs = it->second;
- }
- else {
- Wire *wire = module->addWire(NEW_ID, GetSize(w));
- if (blackbox)
- wire->set_bool_attribute(ID(abc9_padding));
- rhs = wire;
- cell->setPort(port_name, rhs);
- }
- }
- }
-
- cell->attributes["\\abc9_box_seq"] = box_list.size();
- //log_debug("%s.%s is box %d\n", log_id(module), log_id(cell), box_list.size());
- box_list.emplace_back(cell);
- }
- log_assert(!box_list.empty());
-
- RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
- log_assert(holes_module);
- holes_module->set_bool_attribute("\\abc9_holes");
-
- dict<IdString, Cell*> cell_cache;
- dict<IdString, std::vector<IdString>> box_ports;
-
- int port_id = 1;
- for (auto cell : box_list) {
- RTLIL::Module* orig_box_module = design->module(cell->type);
- log_assert(orig_box_module);
- IdString derived_name = orig_box_module->derive(design, cell->parameters);
- RTLIL::Module* box_module = design->module(derived_name);
- cell->type = derived_name;
- cell->parameters.clear();
-
- int box_inputs = 0;
- auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
- Cell *holes_cell = r.first->second;
- if (r.second && box_module->get_bool_attribute("\\whitebox")) {
- holes_cell = holes_module->addCell(cell->name, cell->type);
- holes_cell->parameters = cell->parameters;
- r.first->second = holes_cell;