- if (w->port_output)
- for (int i = 0; i < GetSize(w); i++) {
- if (GetSize(w) == 1)
- holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
- else
- holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
- holes_wire->port_output = true;
- holes_wire->port_id = port_id++;
- holes_module->ports.push_back(holes_wire->name);
- if (holes_cell)
- port_sig.append(holes_wire);
+ }
+ else // box_module is a blackbox
+ log_assert(holes_cell == nullptr);
+ }
+
+ for (auto port_name : box_ports.at(cell->type)) {
+ RTLIL::Wire *w = box_module->wire(port_name);
+ log_assert(w);
+ if (!w->port_output)
+ continue;
+ Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(port_name)), GetSize(w));
+ holes_wire->port_output = true;
+ holes_wire->port_id = port_id++;
+ holes_module->ports.push_back(holes_wire->name);
+ if (holes_cell) // whitebox
+ holes_module->connect(holes_wire, holes_cell->getPort(port_name));
+ else // blackbox
+ holes_module->connect(holes_wire, Const(State::S0, GetSize(w)));
+ }
+ }
+}
+
+void prep_delays(RTLIL::Design *design)
+{
+ std::set<int> delays;
+ pool<Module*> flops;
+ std::vector<Cell*> cells;
+ dict<IdString,dict<IdString,std::vector<int>>> requireds_cache;
+ for (auto module : design->selected_modules()) {
+ if (module->processes.size() > 0) {
+ log("Skipping module %s as it contains processes.\n", log_id(module));
+ continue;
+ }
+
+ cells.clear();
+ for (auto cell : module->cells()) {
+ if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_), ID($__ABC9_DELAY)))
+ continue;
+
+ RTLIL::Module* inst_module = module->design->module(cell->type);
+ if (!inst_module)
+ continue;
+ if (!inst_module->get_blackbox_attribute())
+ continue;
+ if (inst_module->get_bool_attribute(ID(abc9_flop))) {
+ IdString derived_type = inst_module->derive(design, cell->parameters);
+ inst_module = design->module(derived_type);
+ log_assert(inst_module);
+ flops.insert(inst_module);
+ continue; // because all flop required times
+ // will be captured in the flop box
+ }
+ if (inst_module->attributes.count(ID(abc9_box_id)))
+ continue;
+ cells.emplace_back(cell);
+ }
+
+ delays.clear();
+ for (auto cell : cells) {
+ RTLIL::Module* inst_module = module->design->module(cell->type);
+ log_assert(inst_module);
+ auto &cell_requireds = requireds_cache[cell->type];
+ for (auto &conn : cell->connections_) {
+ auto port_wire = inst_module->wire(conn.first);
+ if (!port_wire->port_input)
+ continue;
+
+ auto r = cell_requireds.insert(conn.first);
+ auto &requireds = r.first->second;
+ if (r.second) {
+ auto it = port_wire->attributes.find("\\abc9_required");
+ if (it == port_wire->attributes.end())
+ continue;
+ if (it->second.flags == 0) {
+ int delay = it->second.as_int();
+ delays.insert(delay);
+ requireds.emplace_back(delay);
+ }