+
+\frame{\frametitle{Example: 7 banks, 4-way mux, 160 pins}
+ \begin{center}
+ \includegraphics[height=1.5in]{example_pinmux.jpg}\\
+ 7 "banks" with separate VCC. Each no more than 32 bits
+ \end{center}
+ \begin{itemize}
+ \item { \bf 17,500 lines of auto-generated HDL (and climbing)}
+ \item { \bf 12,500 lines of auto-generated Summary/Analysis}
+ \item Technical Reference Manual expected to be 100+ pages
+ \end{itemize}
+}
+
+
+\frame{\frametitle{Reduce workload, reduce duplication, reduce risk and cost}
+
+ \begin{itemize}
+ \item Auto-generate everything: documentation, code, libraries etc.\\
+ (including device-tree files, FreeBSD / Linux / RTOS kernel
+ drivers, Arduino, libopencm3 and other EC firmware libraries)
+ \vspace{4pt}
+ \item Standardise: similar to PLIC, propose GPIO and Pinmux\\
+ saves engineering effort, design effort and much more
+ \vspace{4pt}
+ \item Standardise format of configuration registers:
+ saves code duplication effort (multiple software environments)
+ \vspace{4pt}
+ \item Add support for multiple code formats: Chisel3 (SiFive IOF),
+ BSV (Bluespec), Verilog, VHDL, MyHDL.
+ \vspace{4pt}
+ \item Multiple auto-generated code-formats permits cross-validation:\\
+ auto-generated test suite in one HDL can validate a muxer
+ generated for a different target HDL.
+ \vspace{4pt}
+ \end{itemize}
+}
+
+
+\frame{\frametitle{Design Spec and Scenario Analysis}