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add Makefile for verilog compilation
[rv32.git]
/
pipestage.py
diff --git
a/pipestage.py
b/pipestage.py
index 91087a0ae54e9eae0a80739aa8a41be2edbe176d..4ec0da059d159ae8aac29f4505098de5990d02b7 100644
(file)
--- a/
pipestage.py
+++ b/
pipestage.py
@@
-66,16
+66,16
@@
class SimplePipelineExample(SimplePipeline):
self.n = ~self._loopback
def stage1(self):
self.n = ~self._loopback
def stage1(self):
- self.n = self.n
+ self.n = self.n
+ 1
def stage2(self):
def stage2(self):
- self.n = self.n
+ self.n = self.n
<< 1
def stage3(self):
def stage3(self):
- self.n = self.n
+ self.n =
~
self.n
def stage4(self):
def stage4(self):
- self._pipe.sync += self._loopback.eq(self.n)
+ self._pipe.sync += self._loopback.eq(self.n
+ 3
)
class PipeModule(Module):
def __init__(self):
class PipeModule(Module):
def __init__(self):