+OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
+layout generation flow (RTL-to-GDS).
+
+* <https://theopenroadproject.org/>
+
+# Other RISC-V GPU attempts
+
+* <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
+
+* <http://bjump.org/manycore/>
+
+* <https://resharma.github.io/RISCV32-GPU/>
+
+TODO: Get in touch and discuss collaboration
+
+# Tests, Benchmarks, Conformance, Compliance, Verification, etc.
+
+## RISC-V Tests
+
+RISC-V Foundation is in the process of creating an official conformance
+test. It's still in development as far as I can tell.
+
+* //TODO LINK TO RISC-V CONFORMANCE TEST
+
+## IEEE 754 Testing/Emulation
+
+IEEE 754 has no official tests for floating-point but there are
+well-known third party tools to check such as John Hauser's TestFloat.
+
+There is also his SoftFloat library, which is a software emulation
+library for IEEE 754.
+
+* <http://www.jhauser.us/arithmetic/>
+
+Jacob is also working on an IEEE 754 software emulation library written
+in Rust which also has Python bindings:
+
+* Source: <https://salsa.debian.org/Kazan-team/simple-soft-float>
+* Crate: <https://crates.io/crates/simple-soft-float>
+* Autogenerated Docs: <https://docs.rs/simple-soft-float/>
+
+A cool paper I came across in my research is "IeeeCC754++ : An Advanced
+Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
+
+* Direct link to PDF:
+ <http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf>
+
+## Khronos Tests
+
+OpenCL Conformance Tests
+
+* <https://github.com/KhronosGroup/OpenCL-CTS>
+
+Vulkan Conformance Tests
+
+* <https://github.com/KhronosGroup/VK-GL-CTS>
+
+MAJOR NOTE: We are **not** allowed to say we are compliant with any of
+the Khronos standards until we actually make an official submission,
+do the paperwork, and pay the relevant fees.
+
+## Formal Verification
+
+Formal verification of Libre RISC-V ensures that it is bug-free in
+regards to what we specify. Of course, it is important to do the formal
+verification as a final step in the development process before we produce
+thousands or millions of silicon.
+
+* Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
+
+* Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
+* Minisail <https://www.isa-afp.org/entries/MiniSail.html> - compiler
+ for SAIL into c
+
+Some learning resources I found in the community:
+
+* ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
+ tutorial for beginners and many exercises/quizzes/slides:
+ <http://zipcpu.com/tutorial/>
+* Western Digital's SweRV CPU blog (I recommend looking at all their
+ posts): <https://tomverbeure.github.io/>
+* <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
+* <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
+
+## Automation
+
+* <https://www.ohwr.org/project/wishbone-gen>
+
+# LLVM
+
+## Adding new instructions:
+
+* <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
+
+# Branch Prediction
+
+* <https://danluu.com/branch-prediction/>
+
+# Python RTL Tools
+
+* [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
+* [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
+ An SOC builder written in Python Migen DSL. Allows you to generate functional
+ RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
+ and parameterizeable CSRs.
+* [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
+* There is a great guy, Robert Baruch, who has a good
+ [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
+ He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put
+ [the code](https://github.com/RobertBaruch/n6800) and
+ [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
+ online.
+* [Minerva](https://github.com/lambdaconcept/minerva)
+ An SOC written in Python nMigen DSL
+* Minerva example using nmigen-soc
+ <https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
+* [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
+* <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
+* <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
+
+# Other
+
+* <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
+* <https://codeberg.org/tok/librecell> Libre Cell Library
+* <https://wiki.f-si.org/index.php/FSiC2019>
+* <https://fusesoc.net>
+* <https://www.lowrisc.org/open-silicon/>
+* <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
+* <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
+* <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
+ Synchronous Resets? Asynchronous Resets? I am so confused! How will I
+ ever know which to use? by Clifford E. Cummings
+* <http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf>
+ Clock Domain Crossing (CDC) Design & Verification Techniques Using
+ SystemVerilog, by Clifford E. Cummings
+ In particular, see section 5.8.2: Multi-bit CDC signal passing using
+ 1-deep / 2-register FIFO synchronizer.
+* <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
+ Understanding Latency Hiding on GPUs, by Vasily Volkov
+* Efabless "Openlane" <https://github.com/efabless/openlane>
+* example of openlane with nmigen
+ <https://github.com/lethalbit/nmigen/tree/openlane>
+* Co-simulation plugin for verilator, transferring to ECP5
+ <https://github.com/vmware/cascade>
+* Multi-read/write ported memories
+ <https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html>
+* Data-dependent fail-on-first aka "Fault-tolerant speculative vectorisation"
+ <https://arxiv.org/pdf/1803.06185.pdf>
+* OpenPOWER Foundation Membership
+ <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
+* Clock switching (and formal verification)
+ <https://zipcpu.com/formal/2018/05/31/clkswitch.html>
+* Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
+* Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
+* Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
+<https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
+
+# Real/Physical Projects
+
+* [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
+* <https://chips4makers.io/blog/>
+* <https://hackaday.io/project/7817-zynqberry>
+* <https://github.com/efabless/raven-picorv32>
+* <https://efabless.com>
+* <https://efabless.com/design_catalog/default>
+* <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
+* <https://mshahrad.github.io/openpiton-asplos16.html>
+
+# ASIC tape-out pricing
+
+* <https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf>
+
+# Funding
+
+* <https://toyota-ai.ventures/>
+* [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
+
+# Good Programming/Design Practices
+
+* [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
+* [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
+* <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
+* [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
+
+* <https://youtu.be/o5Ihqg72T3c>
+* <http://flopoco.gforge.inria.fr/>
+* Fundamentals of Modern VLSI Devices
+ <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
+
+# 12 skills summary
+
+* <https://www.crnhq.org/cr-kit/>
+
+# Analog Simulation
+
+* <https://github.com/Isotel/mixedsim>
+* <http://www.vlsiacademy.org/open-source-cad-tools.html>
+* <http://ngspice.sourceforge.net/adms.html>
+* <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
+
+# Libre-SOC Standards
+
+This list auto-generated from a page tag "standards":
+
+[[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
+
+# Server setup
+
+* [[resources/server-setup/web-server]]
+* [[resources/server-setup/git-mirroring]]
+* [[resources/server-setup/nagios-monitoring]]
+
+# Testbeds
+
+* <https://www.fed4fire.eu/testbeds/>
+
+# Really Useful Stuff
+
+* <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
+* <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>
+
+# Digilent Arty
+
+* https://store.digilentinc.com/pmod-sf3-32-mb-serial-nor-flash/
+* https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/
+* https://store.digilentinc.com/pmod-vga-video-graphics-array/
+* https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
+* https://store.digilentinc.com/pmod-rtcc-real-time-clock-calendar/
+* https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
+
+# CircuitJS experiments
+
+* [[resources/high-speed-serdes-in-circuitjs]]
+
+# Logic Simulator 2
+* <https://github.com/dkilfoyle/logic2>
+[Live web version](https://dkilfoyle.github.io/logic2/)
+
+> ## Features
+> 1. Micro-subset verilog-like DSL for coding the array of logic gates (parsed using Antlr)
+> 2. Monaco-based code editor with automatic linting/error reporting, smart indentation, code folding, hints
+> 3. IDE docking ui courtesy of JupyterLab's Lumino widgets
+> 4. Schematic visualisation courtesy of d3-hwschematic
+> 5. Testbench simulation with graphical trace output and schematic animation
+> 6. Circuit description as gates, boolean logic or verilog behavioural model
+> 7. Generate arbitrary outputs from truth table and Sum of Products or Karnaugh Map
+
+[from the GitHub page. As of 2021/03/29]
+
+# ASIC Timing and Design flow resources
+
+* <https://www.linkedin.com/pulse/asic-design-flow-introduction-timing-constraints-mahmoud-abdellatif/>
+* <https://www.icdesigntips.com/2020/10/setup-and-hold-time-explained.html>
+* <https://www.vlsiguide.com/2018/07/clock-tree-synthesis-cts.html>
+* <https://en.wikipedia.org/wiki/Frequency_divider>
+
+# Geometric Haskell Library
+
+* <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/GeometricAlgebra.hs>
+* <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/PGA.hs>
+* <https://arxiv.org/pdf/1501.06511.pdf>
+* <https://bivector.net/index.html>
+
+# TODO investigate