+# Testbeds
+
+* <https://www.fed4fire.eu/testbeds/>
+
+# Really Useful Stuff
+
+* <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
+* <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>
+
+# Digilent Arty
+
+* https://store.digilentinc.com/pmod-sf3-32-mb-serial-nor-flash/
+* https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/
+* https://store.digilentinc.com/pmod-vga-video-graphics-array/
+* https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
+* https://store.digilentinc.com/pmod-rtcc-real-time-clock-calendar/
+* https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
+
+# CircuitJS experiments
+
+* [[resources/high-speed-serdes-in-circuitjs]]
+
+# Logic Simulator 2
+* <https://github.com/dkilfoyle/logic2>
+[Live web version](https://dkilfoyle.github.io/logic2/)
+
+> ## Features
+> 1. Micro-subset verilog-like DSL for coding the array of logic gates (parsed using Antlr)
+> 2. Monaco-based code editor with automatic linting/error reporting, smart indentation, code folding, hints
+> 3. IDE docking ui courtesy of JupyterLab's Lumino widgets
+> 4. Schematic visualisation courtesy of d3-hwschematic
+> 5. Testbench simulation with graphical trace output and schematic animation
+> 6. Circuit description as gates, boolean logic or verilog behavioural model
+> 7. Generate arbitrary outputs from truth table and Sum of Products or Karnaugh Map
+
+[from the GitHub page. As of 2021/03/29]
+
+# ASIC Timing and Design flow resources
+
+* <https://www.linkedin.com/pulse/asic-design-flow-introduction-timing-constraints-mahmoud-abdellatif/>
+* <https://www.icdesigntips.com/2020/10/setup-and-hold-time-explained.html>
+* <https://www.vlsiguide.com/2018/07/clock-tree-synthesis-cts.html>
+* <https://en.wikipedia.org/wiki/Frequency_divider>
+
+# Geometric Haskell Library
+
+* <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/GeometricAlgebra.hs>
+* <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/PGA.hs>
+* <https://arxiv.org/pdf/1501.06511.pdf>
+* <https://bivector.net/index.html>
+
+# Handy Compiler Algorithms for SimpleV
+
+Requires aligned registers:
+
+* [Graph Coloring Register Allocation for Processors with Multi-Register Operands](https://dl.acm.org/doi/pdf/10.1145/93548.93552)
+
+More general:
+
+* [Retargetable Graph-Coloring Register Allocation for Irregular Architectures](https://user.it.uu.se/~svenolof/wpo/AllocSCOPES2003.20030626b.pdf)
+
+# TODO investigate
+
+```
+ https://www.nextplatform.com/2022/08/22/the-expanding-cxl-memory-hierarchy-is-inevitable-and-good-enough/
+ https://github.com/idea-fasoc/OpenFASOC
+ https://www.quicklogic.com/2020/06/18/the-tipping-point/
+ https://www.quicklogic.com/blog/
+ https://www.quicklogic.com/2020/09/15/why-open-source-ecosystems-make-good-business-sense/
+ https://www.quicklogic.com/qorc/
+ https://en.wikipedia.org/wiki/RAD750
+ The RAD750 system has a price that is comparable to the RAD6000, the latter of which as of 2002 was listed at US$200,000 (equivalent to $284,292 in 2019).
+ https://theamphour.com/525-open-fpga-toolchains-and-machine-learning-with-brian-faith-of-quicklogic/
+ https://github.blog/2021-03-22-open-innovation-winning-strategy-digital-sovereignty-human-progress/
+ https://github.com/olofk/edalize
+ https://github.com/hdl/containers
+ https://twitter.com/OlofKindgren/status/1374848733746192394
+ You might also want to check out https://umarcor.github.io/osvb/index.html
+ https://www.linkedin.com/pulse/1932021-python-now-replaces-tcl-all-besteda-apis-avidan-efody/
+ “TCL has served us well, over the years, allowing us to provide an API, and at the same time ensure nobody will ever use it. I will miss it”.
+ https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/comb-full-adder.html
+ https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/carry4.html
+ FuseSoC is used by MicroWatt and Western Digital cores
+ OpenTitan also uses FuseSoC
+ LowRISC is UK based
+ https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
+ https://cirosantilli.com/x86-paging
+ https://stackoverflow.com/questions/18431261/how-does-x86-paging-work
+ http://denninginstitute.com/modules/vm/red/i486page.html
+ https://m.slashdot.org/story/391021 - mirror neural atrophy results in destruction of empathy
+```