+* <https://www.tdx.cat/bitstream/handle/10803/674224/TCRL1de1.pdf> Vector registers may be
+ made "ultra-wide" (SX Aurora / Cray)
+
+# Other GPU Specifications
+
+*
+* https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf
+* https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf
+* MALI Midgard
+* [Nyuzi](https://github.com/jbush001/NyuziProcessor)
+* VideoCore IV
+* etnaviv
+
+# Other CPUs and ISAs worth considering
+
+* https://en.m.wikipedia.org/wiki/Zilog_Z380
+* Mitch Alsup 66000
+* Hitachi Sh2
+ https://lists.j-core.org/pipermail/j-core/
+ http://shared-ptr.com/sh_insns.html
+* 68080 except Length-Decode is a pig for Multi-Issue
+ http://www.apollo-core.com/index.htm?page=coding&tl=1
+
+# Package Management
+
+* <https://packages.debian.org/search?keywords=proot>
+* <https://github.com/stb-tester/apt2ostree>