+ -- extswsli
+ report "test extswsli";
+ ra <= (others => '0');
+ is_32bit <= '0';
+ right_shift <= '0';
+ arith <= '0';
+ clear_left <= '0';
+ clear_right <= '0';
+ extsw <= '1';
+ extswsli_loop : for i in 0 to 1000 loop
+ rs <= pseudorand(64);
+ shift <= '0' & pseudorand(6);
+ wait for clk_period;
+ behave_ra := rs;
+ behave_ra(63 downto 32) := (others => rs(31));
+ behave_ra := std_ulogic_vector(shift_left(unsigned(behave_ra),
+ to_integer(unsigned(shift))));
+ --report "rs = " & to_hstring(rs);
+ --report "ra = " & to_hstring(ra);
+ --report "shift = " & to_hstring(shift);
+ --report "result = " & to_hstring(carry_out & result);
+ assert behave_ra = result
+ report "bad extswsli expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
+ end loop;
+
+ std.env.finish;