+Surprisingly complex!
+
+# Requirements
+
+"to create a general-purpose libre-licensed pinmux
+module that can be used with a wide range of interfaces that have
+Open-Drain, Push-Pull *and bi-directional* capabilities, as well as
+optional pull-up and pull-down resistors, in an IDENTICAL fashion to
+that of ALL major well-known embedded SoCs from ST Micro, Cypress,
+Texas Instruments, NXP, Rockchip, Allwinner and many many others".
+
+* The IO pad shall have pull-up enable, pull-down enable, variable
+ frequency de-bounce (schmidt trigger), tri-state capability,
+ variable current drive (on input), Open Drain and CMOS Push-Pull.
+* Certain functions shall have the ability to control whether
+ IO pads will be input or output (not the GPIO registers).
+* Number of wires shall be minimised especially in cases where
+ the IO pad (puen, oe) need to change under the control of the
+ function (not the GPIO registers).
+* The amount of latency (gates in between I/O pad and function)
+ shall be minimised
+* There shall be no short-circuits created by multiple input
+ pins trying to drive the same input function
+* There shall be no short-circuits even when functions control
+ when the IO pad is an input.
+
+## Analysis
+
+Questions:
+
+* Can damage occur (to the ASIC) by outputs being short-circuited to outputs
+ in any way?
+ A partial analysis showed that because outputs are one-to-many, there should
+ not be a possibility for that to occur. However what if a function is
+ bi-directional?
+* Is de-bouncing always needed on every input? Is it ok for de-bouncing
+ to be only done on EINT?
+* Can the input mux be turned round and "selector" logic added so that
+ there is no possibility of damage to inputs?
+
+# Images
+
+* [[mygpiomux.jpg]]
+
+# GSoC2018
+
+Introductions:
+
+* Luke Kenneth Casson Leighton (lkcl) - reverse-engineer, software libre
+ advocate, assembly-level programming and disassembly, python, c, c++,
+ gate-level circuit and ASIC design, PCB design and assembly, 3D CAD design,
+ lots of different stuff. Guardian of the EOMA68 Certification Mark,
+ and currently responsible for coordinating the design of a fully Libre
+ RISC-V SoC in collaboration with the RISE Group, IIT Madras, Shakti Project.
+ not much experience at verilog (have done a couple of tutorials).
+* Aurojyoti Das(auro) - graduate student (MSc Electrical - Microelectronics)
+ at TU Delft, Netherlands. C/C++, Verilog, VHDL, SystemVerilog, RTL Design,
+ Logic Verification, Python/Perl/Shell scripting, Analog IC Design (currently learning)
+
+Hardware available:
+
+* lkcl: ZC706
+* xing: zynq-7020 and Xilinx XC7A100T-484 if needed contact him! <higuoxing@gmail.com>
+
+# Discussion and Links
+
+* <https://elinux.org/images/b/b6/Pin_Control_Subsystem_Overview.pdf>
+* <https://lists.librecores.org/pipermail/discussion/2018-February/thread.html>
+* <https://lists.librecores.org/pipermail/discussion/2018-January/000404.html>
+
+# Some Useful Resource
+* <https://github.com/ucb-bar/generator-bootcamp> Interactive tutorial on Scala and Chisel (best one, take it, trust me!)
+* <https://docs.scala-lang.org/tour/tour-of-scala.html> A brief Scala tutorial
+* <https://github.com/ucb-bar/chisel-tutorial> A brief Chisel tutorial
+* <https://github.com/xfguo/tbgen/blob/master/tbgen.py> auto-generated test module for verilog
+* <https://github.com/kdurant/verilog-testbench> described here <https://www.vim.org/scripts/script.php?script_id=4596>
+* <http://agilesoc.com/open-source-projects/svunit/> - SVunit - unit testing for verilog
+* [FPGA Overview](http://www.springer.com/cda/content/document/cda_downloaddocument/9781461435938-c2.pdf?SGWID=0-0-45-1333135-p174308376) Useful in writing GPIO related codes...
+
+# Pinouts Specification
+
+Covered in [[pinouts]]. The general idea is to target several