+ case X (OP_REG, SB): /* Register direct, byte. */
+ *val = GET_B_REG (rn);
+ break;
+ case X (OP_REG, SW): /* Register direct, word. */
+ *val = GET_W_REG (rn);
+ break;
+ case X (OP_REG, SL): /* Register direct, long. */
+ *val = GET_L_REG (rn);
+ break;
+ case X (OP_IMM, SB): /* Immediate, byte. */
+ case X (OP_IMM, SW): /* Immediate, word. */
+ case X (OP_IMM, SL): /* Immediate, long. */
+ *val = abs;
+ break;
+ case X (OP_POSTINC, SB): /* Register indirect w/post-incr: byte. */
+ t = GET_L_REG (rn);
+ t &= h8_get_mask (sd);
+ r = GET_MEMORY_B (t);
+ if (!twice)
+ t += 1;
+ t = t & h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ *val = r;
+ break;
+ case X (OP_POSTINC, SW): /* Register indirect w/post-incr: word. */
+ t = GET_L_REG (rn);
+ t &= h8_get_mask (sd);
+ r = GET_MEMORY_W (t);
+ if (!twice)
+ t += 2;
+ t = t & h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ *val = r;
+ break;
+ case X (OP_POSTINC, SL): /* Register indirect w/post-incr: long. */
+ t = GET_L_REG (rn);
+ t &= h8_get_mask (sd);
+ r = GET_MEMORY_L (t);
+ if (!twice)
+ t += 4;
+ t = t & h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ *val = r;
+ break;
+
+ case X (OP_POSTDEC, SB): /* Register indirect w/post-decr: byte. */
+ t = GET_L_REG (rn);
+ t &= h8_get_mask (sd);
+ r = GET_MEMORY_B (t);
+ if (!twice)
+ t -= 1;
+ t = t & h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ *val = r;
+ break;
+ case X (OP_POSTDEC, SW): /* Register indirect w/post-decr: word. */
+ t = GET_L_REG (rn);
+ t &= h8_get_mask (sd);
+ r = GET_MEMORY_W (t);
+ if (!twice)
+ t -= 2;
+ t = t & h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ *val = r;
+ break;
+ case X (OP_POSTDEC, SL): /* Register indirect w/post-decr: long. */
+ t = GET_L_REG (rn);
+ t &= h8_get_mask (sd);
+ r = GET_MEMORY_L (t);
+ if (!twice)
+ t -= 4;
+ t = t & h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ *val = r;
+ break;
+
+ case X (OP_PREDEC, SB): /* Register indirect w/pre-decr: byte. */
+ t = GET_L_REG (rn) - 1;
+ t &= h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ *val = GET_MEMORY_B (t);
+ break;
+
+ case X (OP_PREDEC, SW): /* Register indirect w/pre-decr: word. */
+ t = GET_L_REG (rn) - 2;
+ t &= h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ *val = GET_MEMORY_W (t);
+ break;
+
+ case X (OP_PREDEC, SL): /* Register indirect w/pre-decr: long. */
+ t = GET_L_REG (rn) - 4;
+ t &= h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ *val = GET_MEMORY_L (t);
+ break;
+
+ case X (OP_PREINC, SB): /* Register indirect w/pre-incr: byte. */
+ t = GET_L_REG (rn) + 1;
+ t &= h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ *val = GET_MEMORY_B (t);
+ break;
+
+ case X (OP_PREINC, SW): /* Register indirect w/pre-incr: long. */
+ t = GET_L_REG (rn) + 2;
+ t &= h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ *val = GET_MEMORY_W (t);
+ break;
+
+ case X (OP_PREINC, SL): /* Register indirect w/pre-incr: long. */
+ t = GET_L_REG (rn) + 4;
+ t &= h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ *val = GET_MEMORY_L (t);
+ break;
+
+ case X (OP_DISP, SB): /* Register indirect w/displacement: byte. */
+ t = GET_L_REG (rn) + abs;
+ t &= h8_get_mask (sd);
+ *val = GET_MEMORY_B (t);
+ break;
+
+ case X (OP_DISP, SW): /* Register indirect w/displacement: word. */
+ t = GET_L_REG (rn) + abs;
+ t &= h8_get_mask (sd);
+ *val = GET_MEMORY_W (t);
+ break;
+
+ case X (OP_DISP, SL): /* Register indirect w/displacement: long. */
+ t = GET_L_REG (rn) + abs;
+ t &= h8_get_mask (sd);
+ *val =GET_MEMORY_L (t);
+ break;
+
+ case X (OP_MEM, SL): /* Absolute memory address, long. */
+ t = GET_MEMORY_L (abs);
+ t &= h8_get_mask (sd);
+ *val = t;
+ break;
+
+ case X (OP_MEM, SW): /* Absolute memory address, word. */
+ t = GET_MEMORY_W (abs);
+ t &= h8_get_mask (sd);
+ *val = t;
+ break;
+
+ case X (OP_PCREL, SB): /* PC relative (for jump, branch etc). */
+ case X (OP_PCREL, SW):
+ case X (OP_PCREL, SL):
+ case X (OP_PCREL, SN):
+ *val = abs;
+ break;
+
+ case X (OP_MEM, SB): /* Why isn't this implemented? */
+ default:
+ sim_engine_set_run_state (sd, sim_stopped, SIGSEGV);
+ return -1;
+ }
+ return 0; /* Success. */
+}
+
+/* Normal fetch. */
+
+static int
+fetch (SIM_DESC sd, ea_type *arg, int *val)
+{
+ return fetch_1 (sd, arg, val, 0);
+}
+
+/* Fetch which will be followed by a store to the same location.
+ The difference being that we don't want to do a post-increment
+ or post-decrement at this time: we'll do it when we store. */
+
+static int
+fetch2 (SIM_DESC sd, ea_type *arg, int *val)
+{
+ return fetch_1 (sd, arg, val, 1);
+}
+
+/* Simulate a memory store.
+ Return 0 for success, -1 for failure.
+*/
+
+static int
+store_1 (SIM_DESC sd, ea_type *arg, int n, int twice)
+{
+ int rn = arg->reg;
+ int abs = arg->literal;
+ int t;
+
+ switch (arg->type)
+ {
+ /* Indexed register plus displacement mode:
+
+ This new family of addressing modes are similar to OP_DISP
+ (register plus displacement), with two differences:
+ 1) INDEXB uses only the least significant byte of the register,
+ INDEXW uses only the least significant word, and
+ INDEXL uses the entire register (just like OP_DISP).
+ and
+ 2) The displacement value in abs is multiplied by two
+ for SW-sized operations, and by four for SL-size.
+
+ This gives nine possible variations.
+ */
+
+ case X (OP_INDEXB, SB):
+ case X (OP_INDEXB, SW):
+ case X (OP_INDEXB, SL):
+ case X (OP_INDEXW, SB):
+ case X (OP_INDEXW, SW):
+ case X (OP_INDEXW, SL):
+ case X (OP_INDEXL, SB):
+ case X (OP_INDEXL, SW):
+ case X (OP_INDEXL, SL):
+ t = GET_L_REG (rn);
+ switch (OP_KIND (arg->type)) {
+ case OP_INDEXB: t &= 0xff; break;
+ case OP_INDEXW: t &= 0xffff; break;
+ case OP_INDEXL:
+ default: break;
+ }
+ switch (OP_SIZE (arg->type)) {
+ case SB:
+ SET_MEMORY_B ((t * 1 + abs) & h8_get_mask (sd), n);
+ break;
+ case SW:
+ SET_MEMORY_W ((t * 2 + abs) & h8_get_mask (sd), n);
+ break;
+ case SL:
+ SET_MEMORY_L ((t * 4 + abs) & h8_get_mask (sd), n);
+ break;
+ }
+ break;
+
+ case X (OP_REG, SB): /* Register direct, byte. */
+ SET_B_REG (rn, n);
+ break;
+ case X (OP_REG, SW): /* Register direct, word. */
+ SET_W_REG (rn, n);
+ break;
+ case X (OP_REG, SL): /* Register direct, long. */
+ SET_L_REG (rn, n);
+ break;
+
+ case X (OP_PREDEC, SB): /* Register indirect w/pre-decr, byte. */
+ t = GET_L_REG (rn);
+ if (!twice)
+ t -= 1;
+ t &= h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ SET_MEMORY_B (t, n);
+
+ break;
+ case X (OP_PREDEC, SW): /* Register indirect w/pre-decr, word. */
+ t = GET_L_REG (rn);
+ if (!twice)
+ t -= 2;
+ t &= h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ SET_MEMORY_W (t, n);
+ break;
+
+ case X (OP_PREDEC, SL): /* Register indirect w/pre-decr, long. */
+ t = GET_L_REG (rn);
+ if (!twice)
+ t -= 4;
+ t &= h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ SET_MEMORY_L (t, n);
+ break;
+
+ case X (OP_PREINC, SB): /* Register indirect w/pre-incr, byte. */
+ t = GET_L_REG (rn);
+ if (!twice)
+ t += 1;
+ t &= h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ SET_MEMORY_B (t, n);
+
+ break;
+ case X (OP_PREINC, SW): /* Register indirect w/pre-incr, word. */
+ t = GET_L_REG (rn);
+ if (!twice)
+ t += 2;
+ t &= h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ SET_MEMORY_W (t, n);
+ break;
+
+ case X (OP_PREINC, SL): /* Register indirect w/pre-incr, long. */
+ t = GET_L_REG (rn);
+ if (!twice)
+ t += 4;
+ t &= h8_get_mask (sd);
+ SET_L_REG (rn, t);
+ SET_MEMORY_L (t, n);
+ break;
+
+ case X (OP_POSTDEC, SB): /* Register indirect w/post-decr, byte. */
+ t = GET_L_REG (rn) & h8_get_mask (sd);
+ SET_MEMORY_B (t, n);
+ SET_L_REG (rn, t - 1);
+ break;
+
+ case X (OP_POSTDEC, SW): /* Register indirect w/post-decr, word. */
+ t = GET_L_REG (rn) & h8_get_mask (sd);
+ SET_MEMORY_W (t, n);
+ SET_L_REG (rn, t - 2);
+ break;
+
+ case X (OP_POSTDEC, SL): /* Register indirect w/post-decr, long. */
+ t = GET_L_REG (rn) & h8_get_mask (sd);
+ SET_MEMORY_L (t, n);
+ SET_L_REG (rn, t - 4);
+ break;
+
+ case X (OP_POSTINC, SB): /* Register indirect w/post-incr, byte. */
+ t = GET_L_REG (rn) & h8_get_mask (sd);
+ SET_MEMORY_B (t, n);
+ SET_L_REG (rn, t + 1);
+ break;
+
+ case X (OP_POSTINC, SW): /* Register indirect w/post-incr, word. */
+ t = GET_L_REG (rn) & h8_get_mask (sd);
+ SET_MEMORY_W (t, n);
+ SET_L_REG (rn, t + 2);
+ break;
+
+ case X (OP_POSTINC, SL): /* Register indirect w/post-incr, long. */
+ t = GET_L_REG (rn) & h8_get_mask (sd);
+ SET_MEMORY_L (t, n);
+ SET_L_REG (rn, t + 4);
+ break;
+
+ case X (OP_DISP, SB): /* Register indirect w/displacement, byte. */
+ t = GET_L_REG (rn) + abs;
+ t &= h8_get_mask (sd);
+ SET_MEMORY_B (t, n);
+ break;
+
+ case X (OP_DISP, SW): /* Register indirect w/displacement, word. */
+ t = GET_L_REG (rn) + abs;
+ t &= h8_get_mask (sd);
+ SET_MEMORY_W (t, n);
+ break;
+
+ case X (OP_DISP, SL): /* Register indirect w/displacement, long. */
+ t = GET_L_REG (rn) + abs;
+ t &= h8_get_mask (sd);
+ SET_MEMORY_L (t, n);
+ break;
+
+
+ case X (OP_MEM, SB): /* Why isn't this implemented? */
+ case X (OP_MEM, SW): /* Why isn't this implemented? */
+ case X (OP_MEM, SL): /* Why isn't this implemented? */
+ default:
+ sim_engine_set_run_state (sd, sim_stopped, SIGSEGV);
+ return -1;
+ }
+ return 0;
+}
+
+/* Normal store. */
+
+static int
+store (SIM_DESC sd, ea_type *arg, int n)
+{
+ return store_1 (sd, arg, n, 0);
+}
+
+/* Store which follows a fetch from the same location.
+ The difference being that we don't want to do a pre-increment
+ or pre-decrement at this time: it was already done when we fetched. */
+
+static int
+store2 (SIM_DESC sd, ea_type *arg, int n)
+{
+ return store_1 (sd, arg, n, 1);
+}
+
+static union
+{
+ short int i;
+ struct
+ {
+ char low;
+ char high;
+ }
+ u;
+} littleendian;
+
+/* Flag to be set whenever a new SIM_DESC object is created. */
+static int init_pointers_needed = 1;
+
+static void
+init_pointers (SIM_DESC sd)
+{
+ if (init_pointers_needed)
+ {
+ int i;
+
+ littleendian.i = 1;
+
+ if (h8300smode && !h8300_normal_mode)
+ memory_size = H8300S_MSIZE;
+ else if (h8300hmode && !h8300_normal_mode)
+ memory_size = H8300H_MSIZE;
+ else
+ memory_size = H8300_MSIZE;
+ /* `msize' must be a power of two. */
+ if ((memory_size & (memory_size - 1)) != 0)
+ {
+ (*sim_callback->printf_filtered)
+ (sim_callback,
+ "init_pointers: bad memory size %d, defaulting to %d.\n",
+ memory_size, memory_size = H8300S_MSIZE);
+ }
+
+ if (h8_get_memory_buf (sd))
+ free (h8_get_memory_buf (sd));
+ if (h8_get_cache_idx_buf (sd))
+ free (h8_get_cache_idx_buf (sd));
+ if (h8_get_eightbit_buf (sd))
+ free (h8_get_eightbit_buf (sd));
+
+ h8_set_memory_buf (sd, (unsigned char *)
+ calloc (sizeof (char), memory_size));
+ h8_set_cache_idx_buf (sd, (unsigned short *)
+ calloc (sizeof (short), memory_size));
+ sd->memory_size = memory_size;
+ h8_set_eightbit_buf (sd, (unsigned char *) calloc (sizeof (char), 256));
+
+ h8_set_mask (sd, memory_size - 1);
+
+ memset (h8_get_reg_buf (sd), 0, sizeof (((STATE_CPU (sd, 0))->regs)));
+
+ for (i = 0; i < 8; i++)
+ {
+ /* FIXME: rewrite using local buffer. */
+ unsigned char *p = (unsigned char *) (h8_get_reg_buf (sd) + i);
+ unsigned char *e = (unsigned char *) (h8_get_reg_buf (sd) + i + 1);
+ unsigned short *q = (unsigned short *) (h8_get_reg_buf (sd) + i);
+ unsigned short *u = (unsigned short *) (h8_get_reg_buf (sd) + i + 1);
+ h8_set_reg (sd, i, 0x00112233);
+
+ while (p < e)
+ {
+ if (*p == 0x22)
+ breg[i] = p;
+ if (*p == 0x33)
+ breg[i + 8] = p;
+ if (*p == 0x11)
+ breg[i + 16] = p;
+ if (*p == 0x00)
+ breg[i + 24] = p;
+ p++;
+ }
+
+ wreg[i] = wreg[i + 8] = 0;
+ while (q < u)
+ {
+ if (*q == 0x2233)
+ {
+ wreg[i] = q;
+ }
+ if (*q == 0x0011)
+ {
+ wreg[i + 8] = q;
+ }
+ q++;
+ }
+
+ if (wreg[i] == 0 || wreg[i + 8] == 0)
+ (*sim_callback->printf_filtered) (sim_callback,
+ "init_pointers: internal error.\n");
+
+ h8_set_reg (sd, i, 0);
+ lreg[i] = h8_get_reg_buf (sd) + i;
+ }
+
+ /* Note: sim uses pseudo-register ZERO as a zero register. */
+ lreg[ZERO_REGNUM] = h8_get_reg_buf (sd) + ZERO_REGNUM;
+ init_pointers_needed = 0;
+
+ /* Initialize the seg registers. */
+ if (!sd->sim_cache)
+ set_simcache_size (sd, CSIZE);
+ }
+}
+
+/* Grotty global variable for use by control_c signal handler. */
+static SIM_DESC control_c_sim_desc;
+
+static void
+control_c (int sig)
+{
+ sim_engine_set_run_state (control_c_sim_desc, sim_stopped, SIGINT);
+}
+
+int
+sim_stop (SIM_DESC sd)
+{
+ /* FIXME: use a real signal value. */
+ sim_engine_set_run_state (sd, sim_stopped, SIGINT);
+ return 1;
+}
+
+#define OBITOP(name, f, s, op) \
+case O (name, SB): \
+{ \
+ int m, tmp; \
+ \
+ if (f) \
+ if (fetch (sd, &code->dst, &ea)) \
+ goto end; \
+ if (fetch (sd, &code->src, &tmp)) \
+ goto end; \
+ m = 1 << (tmp & 7); \
+ op; \
+ if (s) \
+ if (store (sd, &code->dst,ea)) \
+ goto end; \
+ goto next; \
+}
+
+void
+sim_resume (SIM_DESC sd, int step, int siggnal)
+{
+ static int init1;
+ int cycles = 0;
+ int insts = 0;
+ int tick_start = get_now ();
+ void (*prev) ();
+ int poll_count = 0;
+ int res;
+ int tmp;
+ int rd;
+ int ea;
+ int bit;
+ int pc;
+ int c, nz, v, n, u, h, ui, intMaskBit;
+ int trace, intMask;
+ int oldmask;
+ enum sim_stop reason;
+ int sigrc;
+
+ init_pointers (sd);
+
+ control_c_sim_desc = sd;
+ prev = signal (SIGINT, control_c);
+
+ if (step)
+ {
+ sim_engine_set_run_state (sd, sim_stopped, SIGTRAP);
+ }
+ else
+ {
+ sim_engine_set_run_state (sd, sim_running, 0);
+ }
+
+ pc = h8_get_pc (sd);
+
+ /* The PC should never be odd. */
+ if (pc & 0x1)
+ {
+ sim_engine_set_run_state (sd, sim_stopped, SIGBUS);
+ return;
+ }
+
+ /* Get Status Register (flags). */
+ GETSR (sd);
+
+ if (h8300smode) /* Get exr. */
+ {
+ trace = (h8_get_exr (sd) >> 7) & 1;
+ intMask = h8_get_exr (sd) & 7;
+ }
+
+ oldmask = h8_get_mask (sd);
+ if (!h8300hmode || h8300_normal_mode)
+ h8_set_mask (sd, 0xffff);
+ do
+ {
+ unsigned short cidx;
+ decoded_inst *code;
+
+ top:
+ cidx = h8_get_cache_idx (sd, pc);
+ if (cidx == (unsigned short) -1 ||
+ cidx >= sd->sim_cache_size)
+ goto illegal;
+
+ code = sd->sim_cache + cidx;
+
+#if ADEBUG
+ if (debug)
+ {
+ printf ("%x %d %s\n", pc, code->opcode,
+ code->op ? code->op->name : "**");
+ }
+ h8_increment_stats (sd, code->opcode);
+#endif
+
+ if (code->opcode)
+ {
+ cycles += code->cycles;
+ insts++;
+ }
+
+ switch (code->opcode)
+ {
+ case 0:
+ /*
+ * This opcode is a fake for when we get to an
+ * instruction which hasnt been compiled
+ */
+ compile (sd, pc);
+ goto top;
+ break;
+
+ case O (O_MOVAB, SL):
+ case O (O_MOVAW, SL):
+ case O (O_MOVAL, SL):
+ /* 1) Evaluate 2nd argument (dst).
+ 2) Mask / zero extend according to whether 1st argument (src)
+ is INDEXB, INDEXW, or INDEXL.
+ 3) Left-shift the result by 0, 1 or 2, according to size of mova
+ (mova/b, mova/w, mova/l).
+ 4) Add literal value of 1st argument (src).
+ 5) Store result in 3rd argument (op3).
+ */
+
+ /* Alas, since this is the only instruction with 3 arguments,
+ decode doesn't handle them very well. Some fix-up is required.
+
+ a) The size of dst is determined by whether src is
+ INDEXB or INDEXW. */
+
+ if (OP_KIND (code->src.type) == OP_INDEXB)
+ code->dst.type = X (OP_KIND (code->dst.type), SB);
+ else if (OP_KIND (code->src.type) == OP_INDEXW)
+ code->dst.type = X (OP_KIND (code->dst.type), SW);
+
+ /* b) If op3 == null, then this is the short form of the insn.
+ Dst is the dispreg of src, and op3 is the 32-bit form
+ of the same register.
+ */
+
+ if (code->op3.type == 0)
+ {
+ /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
+ We get to compose dst and op3 as follows:
+
+ op3 is a 32-bit register, ID == src.reg.
+ dst is the same register, but 8 or 16 bits
+ depending on whether src is INDEXB or INDEXW.
+ */
+
+ code->op3.type = X (OP_REG, SL);
+ code->op3.reg = code->src.reg;
+ code->op3.literal = 0;
+
+ if (OP_KIND (code->src.type) == OP_INDEXB)
+ {
+ code->dst.type = X (OP_REG, SB);
+ code->dst.reg = code->op3.reg + 8;
+ }
+ else
+ code->dst.type = X (OP_REG, SW);
+ }
+
+ if (fetch (sd, &code->dst, &ea))
+ goto end;
+
+ switch (OP_KIND (code->src.type)) {
+ case OP_INDEXB: ea = ea & 0xff; break;
+ case OP_INDEXW: ea = ea & 0xffff; break;
+ case OP_INDEXL: break;
+ default: goto illegal;
+ }
+
+ switch (code->opcode) {
+ case O (O_MOVAB, SL): break;
+ case O (O_MOVAW, SL): ea = ea << 1; break;
+ case O (O_MOVAL, SL): ea = ea << 2; break;
+ default: goto illegal;
+ }
+
+ ea = ea + code->src.literal;
+
+ if (store (sd, &code->op3, ea))
+ goto end;
+
+ goto next;
+
+ case O (O_SUBX, SB): /* subx, extended sub */
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+ if (fetch (sd, &code->src, &ea))
+ goto end;
+ ea = -(ea + C);
+ res = rd + ea;
+ goto alu8;
+
+ case O (O_SUBX, SW): /* subx, extended sub */
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+ if (fetch (sd, &code->src, &ea))
+ goto end;
+ ea = -(ea + C);
+ res = rd + ea;
+ goto alu16;
+
+ case O (O_SUBX, SL): /* subx, extended sub */
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+ if (fetch (sd, &code->src, &ea))
+ goto end;
+ ea = -(ea + C);
+ res = rd + ea;
+ goto alu32;
+
+ case O (O_ADDX, SB): /* addx, extended add */
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+ if (fetch (sd, &code->src, &ea))
+ goto end;
+ ea = ea + C;
+ res = rd + ea;
+ goto alu8;
+
+ case O (O_ADDX, SW): /* addx, extended add */
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+ if (fetch (sd, &code->src, &ea))
+ goto end;
+ ea = ea + C;
+ res = rd + ea;
+ goto alu16;
+
+ case O (O_ADDX, SL): /* addx, extended add */
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+ if (fetch (sd, &code->src, &ea))
+ goto end;
+ ea = ea + C;
+ res = rd + ea;
+ goto alu32;
+
+ case O (O_SUB, SB): /* sub.b */
+ /* Fetch rd and ea. */
+ if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
+ goto end;
+ ea = -ea;
+ res = rd + ea;
+ goto alu8;
+
+ case O (O_SUB, SW): /* sub.w */
+ /* Fetch rd and ea. */
+ if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
+ goto end;
+ ea = -ea;
+ res = rd + ea;
+ goto alu16;
+
+ case O (O_SUB, SL): /* sub.l */
+ /* Fetch rd and ea. */
+ if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
+ goto end;
+ ea = -ea;
+ res = rd + ea;
+ goto alu32;
+
+ case O (O_NEG, SB): /* neg.b */
+ /* Fetch ea. */
+ if (fetch2 (sd, &code->src, &ea))
+ goto end;
+ ea = -ea;
+ rd = 0;
+ res = rd + ea;
+ goto alu8;
+
+ case O (O_NEG, SW): /* neg.w */
+ /* Fetch ea. */
+ if (fetch2 (sd, &code->src, &ea))
+ goto end;
+ ea = -ea;
+ rd = 0;
+ res = rd + ea;
+ goto alu16;
+
+ case O (O_NEG, SL): /* neg.l */
+ /* Fetch ea. */
+ if (fetch2 (sd, &code->src, &ea))
+ goto end;
+ ea = -ea;
+ rd = 0;
+ res = rd + ea;
+ goto alu32;
+
+ case O (O_ADD, SB): /* add.b */
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+ if (fetch (sd, &code->src, &ea))
+ goto end;
+ res = rd + ea;
+ goto alu8;
+
+ case O (O_ADD, SW): /* add.w */
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+ if (fetch (sd, &code->src, &ea))
+ goto end;
+ res = rd + ea;
+ goto alu16;
+
+ case O (O_ADD, SL): /* add.l */
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+ if (fetch (sd, &code->src, &ea))
+ goto end;
+ res = rd + ea;
+ goto alu32;
+
+ case O (O_AND, SB): /* and.b */
+ /* Fetch rd and ea. */
+ if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
+ goto end;
+ res = rd & ea;
+ goto log8;
+
+ case O (O_AND, SW): /* and.w */
+ /* Fetch rd and ea. */
+ if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
+ goto end;
+ res = rd & ea;
+ goto log16;
+
+ case O (O_AND, SL): /* and.l */
+ /* Fetch rd and ea. */
+ if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
+ goto end;
+ res = rd & ea;
+ goto log32;
+
+ case O (O_OR, SB): /* or.b */
+ /* Fetch rd and ea. */
+ if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
+ goto end;
+ res = rd | ea;
+ goto log8;
+
+ case O (O_OR, SW): /* or.w */
+ /* Fetch rd and ea. */
+ if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
+ goto end;
+ res = rd | ea;
+ goto log16;
+
+ case O (O_OR, SL): /* or.l */
+ /* Fetch rd and ea. */
+ if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
+ goto end;
+ res = rd | ea;
+ goto log32;
+
+ case O (O_XOR, SB): /* xor.b */
+ /* Fetch rd and ea. */
+ if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
+ goto end;
+ res = rd ^ ea;
+ goto log8;
+
+ case O (O_XOR, SW): /* xor.w */
+ /* Fetch rd and ea. */
+ if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
+ goto end;
+ res = rd ^ ea;
+ goto log16;
+
+ case O (O_XOR, SL): /* xor.l */
+ /* Fetch rd and ea. */
+ if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
+ goto end;
+ res = rd ^ ea;
+ goto log32;
+
+ case O (O_MOV, SB):
+ if (fetch (sd, &code->src, &res))
+ goto end;
+ if (store (sd, &code->dst, res))
+ goto end;
+ goto just_flags_log8;
+ case O (O_MOV, SW):
+ if (fetch (sd, &code->src, &res))
+ goto end;
+ if (store (sd, &code->dst, res))
+ goto end;
+ goto just_flags_log16;
+ case O (O_MOV, SL):
+ if (fetch (sd, &code->src, &res))
+ goto end;
+ if (store (sd, &code->dst, res))
+ goto end;
+ goto just_flags_log32;
+
+ case O (O_MOVMD, SB): /* movmd.b */
+ ea = GET_W_REG (4);
+ if (ea == 0)
+ ea = 0x10000;
+
+ while (ea--)
+ {
+ rd = GET_MEMORY_B (GET_L_REG (5));
+ SET_MEMORY_B (GET_L_REG (6), rd);
+ SET_L_REG (5, GET_L_REG (5) + 1);
+ SET_L_REG (6, GET_L_REG (6) + 1);
+ SET_W_REG (4, ea);
+ }
+ goto next;
+
+ case O (O_MOVMD, SW): /* movmd.w */
+ ea = GET_W_REG (4);
+ if (ea == 0)
+ ea = 0x10000;
+
+ while (ea--)
+ {
+ rd = GET_MEMORY_W (GET_L_REG (5));
+ SET_MEMORY_W (GET_L_REG (6), rd);
+ SET_L_REG (5, GET_L_REG (5) + 2);
+ SET_L_REG (6, GET_L_REG (6) + 2);
+ SET_W_REG (4, ea);
+ }
+ goto next;
+
+ case O (O_MOVMD, SL): /* movmd.l */
+ ea = GET_W_REG (4);
+ if (ea == 0)
+ ea = 0x10000;
+
+ while (ea--)
+ {
+ rd = GET_MEMORY_L (GET_L_REG (5));
+ SET_MEMORY_L (GET_L_REG (6), rd);
+ SET_L_REG (5, GET_L_REG (5) + 4);
+ SET_L_REG (6, GET_L_REG (6) + 4);
+ SET_W_REG (4, ea);
+ }
+ goto next;
+
+ case O (O_MOVSD, SB): /* movsd.b */
+ /* This instruction implements strncpy, with a conditional branch.
+ r4 contains n, r5 contains src, and r6 contains dst.
+ The 16-bit displacement operand is added to the pc
+ if and only if the end of string is reached before
+ n bytes are transferred. */
+
+ ea = GET_L_REG (4) & 0xffff;
+ if (ea == 0)
+ ea = 0x10000;
+
+ while (ea--)
+ {
+ rd = GET_MEMORY_B (GET_L_REG (5));
+ SET_MEMORY_B (GET_L_REG (6), rd);
+ SET_L_REG (5, GET_L_REG (5) + 1);
+ SET_L_REG (6, GET_L_REG (6) + 1);
+ SET_W_REG (4, ea);
+ if (rd == 0)
+ goto condtrue;
+ }
+ goto next;
+
+ case O (O_EEPMOV, SB): /* eepmov.b */
+ case O (O_EEPMOV, SW): /* eepmov.w */
+ if (h8300hmode || h8300smode)
+ {
+ register unsigned char *_src, *_dst;
+ unsigned int count = ((code->opcode == O (O_EEPMOV, SW))
+ ? h8_get_reg (sd, R4_REGNUM) & 0xffff
+ : h8_get_reg (sd, R4_REGNUM) & 0xff);
+
+ _src = (h8_get_reg (sd, R5_REGNUM) < memory_size
+ ? h8_get_memory_buf (sd) + h8_get_reg (sd, R5_REGNUM)
+ : h8_get_eightbit_buf (sd) +
+ (h8_get_reg (sd, R5_REGNUM) & 0xff));
+ if ((_src + count) >= (h8_get_memory_buf (sd) + memory_size))
+ {
+ if ((_src + count) >= (h8_get_eightbit_buf (sd) + 0x100))
+ goto illegal;
+ }
+ _dst = (h8_get_reg (sd, R6_REGNUM) < memory_size
+ ? h8_get_memory_buf (sd) + h8_get_reg (sd, R6_REGNUM)
+ : h8_get_eightbit_buf (sd) +
+ (h8_get_reg (sd, R6_REGNUM) & 0xff));
+
+ if ((_dst + count) >= (h8_get_memory_buf (sd) + memory_size))
+ {
+ if ((_dst + count) >= (h8_get_eightbit_buf (sd) + 0x100))
+ goto illegal;
+ }
+ memcpy (_dst, _src, count);
+
+ h8_set_reg (sd, R5_REGNUM, h8_get_reg (sd, R5_REGNUM) + count);
+ h8_set_reg (sd, R6_REGNUM, h8_get_reg (sd, R6_REGNUM) + count);
+ h8_set_reg (sd, R4_REGNUM, h8_get_reg (sd, R4_REGNUM) &
+ ((code->opcode == O (O_EEPMOV, SW))
+ ? (~0xffff) : (~0xff)));
+ cycles += 2 * count;
+ goto next;
+ }
+ goto illegal;
+
+ case O (O_ADDS, SL): /* adds (.l) */
+ /* FIXME fetch.
+ * This insn only uses register operands, but still
+ * it would be cleaner to use fetch and store... */
+ SET_L_REG (code->dst.reg,
+ GET_L_REG (code->dst.reg)
+ + code->src.literal);
+
+ goto next;
+
+ case O (O_SUBS, SL): /* subs (.l) */
+ /* FIXME fetch.
+ * This insn only uses register operands, but still
+ * it would be cleaner to use fetch and store... */
+ SET_L_REG (code->dst.reg,
+ GET_L_REG (code->dst.reg)
+ - code->src.literal);
+ goto next;
+
+ case O (O_CMP, SB): /* cmp.b */
+ if (fetch (sd, &code->dst, &rd))
+ goto end;
+ if (fetch (sd, &code->src, &ea))
+ goto end;
+ ea = -ea;
+ res = rd + ea;
+ goto just_flags_alu8;
+
+ case O (O_CMP, SW): /* cmp.w */
+ if (fetch (sd, &code->dst, &rd))
+ goto end;
+ if (fetch (sd, &code->src, &ea))
+ goto end;
+ ea = -ea;
+ res = rd + ea;
+ goto just_flags_alu16;
+
+ case O (O_CMP, SL): /* cmp.l */
+ if (fetch (sd, &code->dst, &rd))
+ goto end;
+ if (fetch (sd, &code->src, &ea))
+ goto end;
+ ea = -ea;
+ res = rd + ea;
+ goto just_flags_alu32;
+
+ case O (O_DEC, SB): /* dec.b */
+ /* FIXME fetch.
+ * This insn only uses register operands, but still
+ * it would be cleaner to use fetch and store... */
+ rd = GET_B_REG (code->src.reg);
+ ea = -1;
+ res = rd + ea;
+ SET_B_REG (code->src.reg, res);
+ goto just_flags_inc8;
+
+ case O (O_DEC, SW): /* dec.w */
+ /* FIXME fetch.
+ * This insn only uses register operands, but still
+ * it would be cleaner to use fetch and store... */
+ rd = GET_W_REG (code->dst.reg);
+ ea = -code->src.literal;
+ res = rd + ea;
+ SET_W_REG (code->dst.reg, res);
+ goto just_flags_inc16;
+
+ case O (O_DEC, SL): /* dec.l */
+ /* FIXME fetch.
+ * This insn only uses register operands, but still
+ * it would be cleaner to use fetch and store... */
+ rd = GET_L_REG (code->dst.reg);
+ ea = -code->src.literal;
+ res = rd + ea;
+ SET_L_REG (code->dst.reg, res);
+ goto just_flags_inc32;
+
+ case O (O_INC, SB): /* inc.b */
+ /* FIXME fetch.
+ * This insn only uses register operands, but still
+ * it would be cleaner to use fetch and store... */
+ rd = GET_B_REG (code->src.reg);
+ ea = 1;
+ res = rd + ea;
+ SET_B_REG (code->src.reg, res);
+ goto just_flags_inc8;
+
+ case O (O_INC, SW): /* inc.w */
+ /* FIXME fetch.
+ * This insn only uses register operands, but still
+ * it would be cleaner to use fetch and store... */
+ rd = GET_W_REG (code->dst.reg);
+ ea = code->src.literal;
+ res = rd + ea;
+ SET_W_REG (code->dst.reg, res);
+ goto just_flags_inc16;
+
+ case O (O_INC, SL): /* inc.l */
+ /* FIXME fetch.
+ * This insn only uses register operands, but still
+ * it would be cleaner to use fetch and store... */
+ rd = GET_L_REG (code->dst.reg);
+ ea = code->src.literal;
+ res = rd + ea;
+ SET_L_REG (code->dst.reg, res);
+ goto just_flags_inc32;
+
+ case O (O_LDC, SB): /* ldc.b */
+ if (fetch (sd, &code->src, &res))
+ goto end;
+ goto setc;
+
+ case O (O_LDC, SW): /* ldc.w */
+ if (fetch (sd, &code->src, &res))
+ goto end;
+
+ /* Word operand, value from MSB, must be shifted. */
+ res >>= 8;
+ goto setc;
+
+ case O (O_LDC, SL): /* ldc.l */
+ if (fetch (sd, &code->src, &res))
+ goto end;
+ switch (code->dst.type) {
+ case X (OP_SBR, SL):
+ h8_set_sbr (sd, res);
+ break;
+ case X (OP_VBR, SL):
+ h8_set_vbr (sd, res);
+ break;
+ default:
+ goto illegal;
+ }
+ goto next;
+
+ case O (O_STC, SW): /* stc.w */
+ case O (O_STC, SB): /* stc.b */
+ if (code->src.type == X (OP_CCR, SB))
+ {
+ BUILDSR (sd);
+ res = h8_get_ccr (sd);
+ }
+ else if (code->src.type == X (OP_EXR, SB) && h8300smode)
+ {
+ if (h8300smode)
+ h8_set_exr (sd, (trace << 7) | intMask);
+ res = h8_get_exr (sd);
+ }
+ else
+ goto illegal;
+
+ /* Word operand, value to MSB, must be shifted. */
+ if (code->opcode == X (O_STC, SW))
+ res <<= 8;
+ if (store (sd, &code->dst, res))
+ goto end;
+ goto next;
+ case O (O_STC, SL): /* stc.l */
+ switch (code->src.type) {
+ case X (OP_SBR, SL):
+ res = h8_get_sbr (sd);
+ break;
+ case X (OP_VBR, SL):
+ res = h8_get_vbr (sd);
+ break;
+ default:
+ goto illegal;
+ }
+ if (store (sd, &code->dst, res))
+ goto end;
+ goto next;
+
+ case O (O_ANDC, SB): /* andc.b */
+ if (code->dst.type == X (OP_CCR, SB))
+ {
+ BUILDSR (sd);
+ rd = h8_get_ccr (sd);
+ }
+ else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
+ {
+ if (h8300smode)
+ h8_set_exr (sd, (trace << 7) | intMask);
+ rd = h8_get_exr (sd);
+ }
+ else
+ goto illegal;
+ ea = code->src.literal;
+ res = rd & ea;
+ goto setc;
+
+ case O (O_ORC, SB): /* orc.b */
+ if (code->dst.type == X (OP_CCR, SB))
+ {
+ BUILDSR (sd);
+ rd = h8_get_ccr (sd);
+ }
+ else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
+ {
+ if (h8300smode)
+ h8_set_exr (sd, (trace << 7) | intMask);
+ rd = h8_get_exr (sd);
+ }
+ else
+ goto illegal;
+ ea = code->src.literal;
+ res = rd | ea;
+ goto setc;
+
+ case O (O_XORC, SB): /* xorc.b */
+ if (code->dst.type == X (OP_CCR, SB))
+ {
+ BUILDSR (sd);
+ rd = h8_get_ccr (sd);
+ }
+ else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
+ {
+ if (h8300smode)
+ h8_set_exr (sd, (trace << 7) | intMask);
+ rd = h8_get_exr (sd);
+ }
+ else
+ goto illegal;
+ ea = code->src.literal;
+ res = rd ^ ea;
+ goto setc;
+
+ case O (O_BRAS, SB): /* bra/s */
+ /* This is basically an ordinary branch, with a delay slot. */
+ if (fetch (sd, &code->src, &res))
+ goto end;
+
+ if ((res & 1) == 0)
+ goto illegal;
+
+ res -= 1;
+
+ /* Execution continues at next instruction, but
+ delayed_branch is set up for next cycle. */
+ h8_set_delayed_branch (sd, code->next_pc + res);
+ pc = code->next_pc;
+ goto end;
+
+ case O (O_BRAB, SB): /* bra rd.b */
+ case O (O_BRAW, SW): /* bra rd.w */
+ case O (O_BRAL, SL): /* bra erd.l */
+ if (fetch (sd, &code->src, &rd))
+ goto end;
+ switch (OP_SIZE (code->opcode)) {
+ case SB: rd &= 0xff; break;
+ case SW: rd &= 0xffff; break;
+ case SL: rd &= 0xffffffff; break;
+ }
+ pc = code->next_pc + rd;
+ goto end;
+
+ case O (O_BRABC, SB): /* bra/bc, branch if bit clear */
+ case O (O_BRABS, SB): /* bra/bs, branch if bit set */
+ case O (O_BSRBC, SB): /* bsr/bc, call if bit clear */
+ case O (O_BSRBS, SB): /* bsr/bs, call if bit set */
+ if (fetch (sd, &code->dst, &rd) ||
+ fetch (sd, &code->src, &bit))
+ goto end;
+
+ if (code->opcode == O (O_BRABC, SB) || /* branch if clear */
+ code->opcode == O (O_BSRBC, SB)) /* call if clear */
+ {
+ if ((rd & (1 << bit))) /* no branch */
+ goto next;
+ }
+ else /* branch/call if set */
+ {
+ if (!(rd & (1 << bit))) /* no branch */
+ goto next;
+ }
+
+ if (fetch (sd, &code->op3, &res)) /* branch */
+ goto end;
+ pc = code->next_pc + res;
+
+ if (code->opcode == O (O_BRABC, SB) ||
+ code->opcode == O (O_BRABS, SB)) /* branch */
+ goto end;
+ else /* call */
+ goto call;
+
+ case O (O_BRA, SN):
+ case O (O_BRA, SL):
+ case O (O_BRA, SW):
+ case O (O_BRA, SB): /* bra, branch always */
+ if (1)
+ goto condtrue;
+ goto next;
+
+ case O (O_BRN, SB): /* brn, ;-/ branch never? */
+ if (0)
+ goto condtrue;
+ goto next;
+
+ case O (O_BHI, SB): /* bhi */
+ if ((C || Z) == 0)
+ goto condtrue;
+ goto next;
+
+
+ case O (O_BLS, SB): /* bls */
+ if ((C || Z))
+ goto condtrue;
+ goto next;
+
+ case O (O_BCS, SB): /* bcs, branch if carry set */
+ if ((C == 1))
+ goto condtrue;
+ goto next;
+
+ case O (O_BCC, SB): /* bcc, branch if carry clear */
+ if ((C == 0))
+ goto condtrue;
+ goto next;
+
+ case O (O_BEQ, SB): /* beq, branch if zero set */
+ if (Z)
+ goto condtrue;
+ goto next;
+ case O (O_BGT, SB): /* bgt */
+ if (((Z || (N ^ V)) == 0))
+ goto condtrue;
+ goto next;
+
+ case O (O_BLE, SB): /* ble */
+ if (((Z || (N ^ V)) == 1))
+ goto condtrue;
+ goto next;
+
+ case O (O_BGE, SB): /* bge */
+ if ((N ^ V) == 0)
+ goto condtrue;
+ goto next;
+ case O (O_BLT, SB): /* blt */
+ if ((N ^ V))
+ goto condtrue;
+ goto next;
+ case O (O_BMI, SB): /* bmi */
+ if ((N))
+ goto condtrue;
+ goto next;
+ case O (O_BNE, SB): /* bne, branch if zero clear */
+ if ((Z == 0))
+ goto condtrue;
+ goto next;
+
+ case O (O_BPL, SB): /* bpl */
+ if (N == 0)
+ goto condtrue;
+ goto next;
+ case O (O_BVC, SB): /* bvc */
+ if ((V == 0))
+ goto condtrue;
+ goto next;
+ case O (O_BVS, SB): /* bvs */
+ if ((V == 1))
+ goto condtrue;
+ goto next;
+
+ /* Trap for Command Line setup. */
+ case O (O_SYS_CMDLINE, SB):
+ {
+ int i = 0; /* Loop counter. */
+ int j = 0; /* Loop counter. */
+ int ind_arg_len = 0; /* Length of each argument. */
+ int no_of_args = 0; /* The no. or cmdline args. */
+ int current_location = 0; /* Location of string. */
+ int old_sp = 0; /* The Initial Stack Pointer. */
+ int no_of_slots = 0; /* No. of slots required on the stack
+ for storing cmdline args. */
+ int sp_move = 0; /* No. of locations by which the stack needs
+ to grow. */
+ int new_sp = 0; /* The final stack pointer location passed
+ back. */
+ int *argv_ptrs; /* Pointers of argv strings to be stored. */
+ int argv_ptrs_location = 0; /* Location of pointers to cmdline
+ args on the stack. */
+ int char_ptr_size = 0; /* Size of a character pointer on
+ target machine. */
+ int addr_cmdline = 0; /* Memory location where cmdline has
+ to be stored. */
+ int size_cmdline = 0; /* Size of cmdline. */
+
+ /* Set the address of 256 free locations where command line is
+ stored. */
+ addr_cmdline = cmdline_location();
+ h8_set_reg (sd, 0, addr_cmdline);
+
+ /* Counting the no. of commandline arguments. */
+ for (i = 0; h8_get_cmdline_arg (sd, i) != NULL; i++)
+ continue;
+
+ /* No. of arguments in the command line. */
+ no_of_args = i;
+
+ /* Current location is just a temporary variable,which we are
+ setting to the point to the start of our commandline string. */
+ current_location = addr_cmdline;
+
+ /* Allocating space for storing pointers of the command line
+ arguments. */
+ argv_ptrs = (int *) malloc (sizeof (int) * no_of_args);
+
+ /* Setting char_ptr_size to the sizeof (char *) on the different
+ architectures. */
+ if ((h8300hmode || h8300smode) && !h8300_normal_mode)
+ {
+ char_ptr_size = 4;
+ }
+ else
+ {
+ char_ptr_size = 2;
+ }
+
+ for (i = 0; i < no_of_args; i++)
+ {
+ ind_arg_len = 0;
+
+ /* The size of the commandline argument. */
+ ind_arg_len = strlen (h8_get_cmdline_arg (sd, i)) + 1;
+
+ /* The total size of the command line string. */
+ size_cmdline += ind_arg_len;
+
+ /* As we have only 256 bytes, we need to provide a graceful
+ exit. Anyways, a program using command line arguments
+ where we cannot store all the command line arguments
+ given may behave unpredictably. */
+ if (size_cmdline >= 256)
+ {
+ h8_set_reg (sd, 0, 0);
+ goto next;
+ }
+ else
+ {
+ /* current_location points to the memory where the next
+ commandline argument is stored. */
+ argv_ptrs[i] = current_location;
+ for (j = 0; j < ind_arg_len; j++)
+ {
+ SET_MEMORY_B ((current_location +
+ (sizeof (char) * j)),
+ *(h8_get_cmdline_arg (sd, i) +
+ sizeof (char) * j));
+ }
+
+ /* Setting current_location to the starting of next
+ argument. */
+ current_location += ind_arg_len;
+ }
+ }
+
+ /* This is the original position of the stack pointer. */
+ old_sp = h8_get_reg (sd, SP_REGNUM);
+
+ /* We need space from the stack to store the pointers to argvs. */
+ /* As we will infringe on the stack, we need to shift the stack
+ pointer so that the data is not overwritten. We calculate how
+ much space is required. */
+ sp_move = (no_of_args) * (char_ptr_size);
+
+ /* The final position of stack pointer, we have thus taken some
+ space from the stack. */
+ new_sp = old_sp - sp_move;
+
+ /* Temporary variable holding value where the argv pointers need
+ to be stored. */
+ argv_ptrs_location = new_sp;
+
+ /* The argv pointers are stored at sequential locations. As per
+ the H8300 ABI. */
+ for (i = 0; i < no_of_args; i++)
+ {
+ /* Saving the argv pointer. */
+ if ((h8300hmode || h8300smode) && !h8300_normal_mode)
+ {
+ SET_MEMORY_L (argv_ptrs_location, argv_ptrs[i]);
+ }
+ else
+ {
+ SET_MEMORY_W (argv_ptrs_location, argv_ptrs[i]);
+ }
+
+ /* The next location where the pointer to the next argv
+ string has to be stored. */
+ argv_ptrs_location += char_ptr_size;
+ }
+
+ /* Required by POSIX, Setting 0x0 at the end of the list of argv
+ pointers. */
+ if ((h8300hmode || h8300smode) && !h8300_normal_mode)
+ {
+ SET_MEMORY_L (old_sp, 0x0);
+ }
+ else
+ {
+ SET_MEMORY_W (old_sp, 0x0);
+ }
+
+ /* Freeing allocated memory. */
+ free (argv_ptrs);
+ for (i = 0; i <= no_of_args; i++)
+ {
+ free (h8_get_cmdline_arg (sd, i));
+ }
+ free (h8_get_command_line (sd));
+
+ /* The no. of argv arguments are returned in Reg 0. */
+ h8_set_reg (sd, 0, no_of_args);
+ /* The Pointer to argv in Register 1. */
+ h8_set_reg (sd, 1, new_sp);
+ /* Setting the stack pointer to the new value. */
+ h8_set_reg (sd, SP_REGNUM, new_sp);
+ }
+ goto next;
+
+ /* System call processing starts. */
+ case O (O_SYS_OPEN, SB):
+ {
+ int len = 0; /* Length of filename. */
+ char *filename; /* Filename would go here. */
+ char temp_char; /* Temporary character */
+ int mode = 0; /* Mode bits for the file. */
+ int open_return; /* Return value of open, file descriptor. */
+ int i; /* Loop counter */
+ int filename_ptr; /* Pointer to filename in cpu memory. */
+
+ /* Setting filename_ptr to first argument of open, */
+ /* and trying to get mode. */
+ if ((h8300sxmode || h8300hmode || h8300smode) && !h8300_normal_mode)
+ {
+ filename_ptr = GET_L_REG (0);
+ mode = GET_MEMORY_L (h8_get_reg (sd, SP_REGNUM) + 4);
+ }
+ else
+ {
+ filename_ptr = GET_W_REG (0);
+ mode = GET_MEMORY_W (h8_get_reg (sd, SP_REGNUM) + 2);
+ }
+
+ /* Trying to find the length of the filename. */
+ temp_char = GET_MEMORY_B (h8_get_reg (sd, 0));
+
+ len = 1;
+ while (temp_char != '\0')
+ {
+ temp_char = GET_MEMORY_B (filename_ptr + len);
+ len++;
+ }
+
+ /* Allocating space for the filename. */
+ filename = (char *) malloc (sizeof (char) * len);
+
+ /* String copying the filename from memory. */
+ for (i = 0; i < len; i++)
+ {
+ temp_char = GET_MEMORY_B (filename_ptr + i);
+ filename[i] = temp_char;
+ }
+
+ /* Callback to open and return the file descriptor. */
+ open_return = sim_callback->open (sim_callback, filename, mode);
+
+ /* Return value in register 0. */
+ h8_set_reg (sd, 0, open_return);
+
+ /* Freeing memory used for filename. */
+ free (filename);
+ }
+ goto next;
+
+ case O (O_SYS_READ, SB):
+ {
+ char *char_ptr; /* Where characters read would be stored. */
+ int fd; /* File descriptor */
+ int buf_size; /* BUF_SIZE parameter in read. */
+ int i = 0; /* Temporary Loop counter */
+ int read_return = 0; /* Return value from callback to
+ read. */
+
+ fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
+ buf_size = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
+
+ char_ptr = (char *) malloc (sizeof (char) * buf_size);
+
+ /* Callback to read and return the no. of characters read. */
+ read_return =
+ sim_callback->read (sim_callback, fd, char_ptr, buf_size);
+
+ /* The characters read are stored in cpu memory. */
+ for (i = 0; i < buf_size; i++)
+ {
+ SET_MEMORY_B ((h8_get_reg (sd, 1) + (sizeof (char) * i)),
+ *(char_ptr + (sizeof (char) * i)));
+ }
+
+ /* Return value in Register 0. */
+ h8_set_reg (sd, 0, read_return);
+
+ /* Freeing memory used as buffer. */
+ free (char_ptr);
+ }
+ goto next;
+
+ case O (O_SYS_WRITE, SB):
+ {
+ int fd; /* File descriptor */
+ char temp_char; /* Temporary character */
+ int len; /* Length of write, Parameter II to write. */
+ int char_ptr; /* Character Pointer, Parameter I of write. */
+ char *ptr; /* Where characters to be written are stored.
+ */
+ int write_return; /* Return value from callback to write. */
+ int i = 0; /* Loop counter */
+
+ fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
+ char_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
+ len = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
+
+ /* Allocating space for the characters to be written. */
+ ptr = (char *) malloc (sizeof (char) * len);
+
+ /* Fetching the characters from cpu memory. */
+ for (i = 0; i < len; i++)
+ {
+ temp_char = GET_MEMORY_B (char_ptr + i);
+ ptr[i] = temp_char;
+ }
+
+ /* Callback write and return the no. of characters written. */
+ write_return = sim_callback->write (sim_callback, fd, ptr, len);
+
+ /* Return value in Register 0. */
+ h8_set_reg (sd, 0, write_return);
+
+ /* Freeing memory used as buffer. */
+ free (ptr);
+ }
+ goto next;
+
+ case O (O_SYS_LSEEK, SB):
+ {
+ int fd; /* File descriptor */
+ int offset; /* Offset */
+ int origin; /* Origin */
+ int lseek_return; /* Return value from callback to lseek. */
+
+ fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
+ offset = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
+ origin = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
+
+ /* Callback lseek and return offset. */
+ lseek_return =
+ sim_callback->lseek (sim_callback, fd, offset, origin);
+
+ /* Return value in register 0. */
+ h8_set_reg (sd, 0, lseek_return);
+ }
+ goto next;
+
+ case O (O_SYS_CLOSE, SB):
+ {
+ int fd; /* File descriptor */
+ int close_return; /* Return value from callback to close. */
+
+ fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
+
+ /* Callback close and return. */
+ close_return = sim_callback->close (sim_callback, fd);
+
+ /* Return value in register 0. */
+ h8_set_reg (sd, 0, close_return);
+ }
+ goto next;
+
+ case O (O_SYS_FSTAT, SB):
+ {
+ int fd; /* File descriptor */
+ struct stat stat_rec; /* Stat record */
+ int fstat_return; /* Return value from callback to stat. */
+ int stat_ptr; /* Pointer to stat record. */
+ char *temp_stat_ptr; /* Temporary stat_rec pointer. */
+
+ fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
+
+ /* Setting stat_ptr to second argument of stat. */
+ stat_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
+
+ /* Callback stat and return. */
+ fstat_return = sim_callback->fstat (sim_callback, fd, &stat_rec);
+
+ /* Have stat_ptr point to starting of stat_rec. */
+ temp_stat_ptr = (char *) (&stat_rec);
+
+ /* Setting up the stat structure returned. */
+ SET_MEMORY_W (stat_ptr, stat_rec.st_dev);
+ stat_ptr += 2;
+ SET_MEMORY_W (stat_ptr, stat_rec.st_ino);
+ stat_ptr += 2;
+ SET_MEMORY_L (stat_ptr, stat_rec.st_mode);
+ stat_ptr += 4;
+ SET_MEMORY_W (stat_ptr, stat_rec.st_nlink);
+ stat_ptr += 2;
+ SET_MEMORY_W (stat_ptr, stat_rec.st_uid);
+ stat_ptr += 2;
+ SET_MEMORY_W (stat_ptr, stat_rec.st_gid);
+ stat_ptr += 2;
+ SET_MEMORY_W (stat_ptr, stat_rec.st_rdev);
+ stat_ptr += 2;
+ SET_MEMORY_L (stat_ptr, stat_rec.st_size);
+ stat_ptr += 4;
+ SET_MEMORY_L (stat_ptr, stat_rec.st_atime);
+ stat_ptr += 8;
+ SET_MEMORY_L (stat_ptr, stat_rec.st_mtime);
+ stat_ptr += 8;
+ SET_MEMORY_L (stat_ptr, stat_rec.st_ctime);
+
+ /* Return value in register 0. */
+ h8_set_reg (sd, 0, fstat_return);
+ }
+ goto next;
+
+ case O (O_SYS_STAT, SB):
+ {
+ int len = 0; /* Length of filename. */
+ char *filename; /* Filename would go here. */
+ char temp_char; /* Temporary character */
+ int filename_ptr; /* Pointer to filename in cpu memory. */
+ struct stat stat_rec; /* Stat record */
+ int stat_return; /* Return value from callback to stat */
+ int stat_ptr; /* Pointer to stat record. */
+ char *temp_stat_ptr; /* Temporary stat_rec pointer. */
+ int i = 0; /* Loop Counter */
+
+ /* Setting filename_ptr to first argument of open. */
+ filename_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
+
+ /* Trying to find the length of the filename. */
+ temp_char = GET_MEMORY_B (h8_get_reg (sd, 0));
+
+ len = 1;
+ while (temp_char != '\0')
+ {
+ temp_char = GET_MEMORY_B (filename_ptr + len);
+ len++;
+ }
+
+ /* Allocating space for the filename. */
+ filename = (char *) malloc (sizeof (char) * len);
+
+ /* String copying the filename from memory. */
+ for (i = 0; i < len; i++)
+ {
+ temp_char = GET_MEMORY_B (filename_ptr + i);
+ filename[i] = temp_char;
+ }
+
+ /* Setting stat_ptr to second argument of stat. */
+ /* stat_ptr = h8_get_reg (sd, 1); */
+ stat_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
+
+ /* Callback stat and return. */
+ stat_return =
+ sim_callback->stat (sim_callback, filename, &stat_rec);
+
+ /* Have stat_ptr point to starting of stat_rec. */
+ temp_stat_ptr = (char *) (&stat_rec);
+
+ /* Freeing memory used for filename. */
+ free (filename);
+
+ /* Setting up the stat structure returned. */
+ SET_MEMORY_W (stat_ptr, stat_rec.st_dev);
+ stat_ptr += 2;
+ SET_MEMORY_W (stat_ptr, stat_rec.st_ino);
+ stat_ptr += 2;
+ SET_MEMORY_L (stat_ptr, stat_rec.st_mode);
+ stat_ptr += 4;
+ SET_MEMORY_W (stat_ptr, stat_rec.st_nlink);
+ stat_ptr += 2;
+ SET_MEMORY_W (stat_ptr, stat_rec.st_uid);
+ stat_ptr += 2;
+ SET_MEMORY_W (stat_ptr, stat_rec.st_gid);
+ stat_ptr += 2;
+ SET_MEMORY_W (stat_ptr, stat_rec.st_rdev);
+ stat_ptr += 2;
+ SET_MEMORY_L (stat_ptr, stat_rec.st_size);
+ stat_ptr += 4;
+ SET_MEMORY_L (stat_ptr, stat_rec.st_atime);
+ stat_ptr += 8;
+ SET_MEMORY_L (stat_ptr, stat_rec.st_mtime);
+ stat_ptr += 8;
+ SET_MEMORY_L (stat_ptr, stat_rec.st_ctime);
+
+ /* Return value in register 0. */
+ h8_set_reg (sd, 0, stat_return);
+ }
+ goto next;
+ /* End of system call processing. */
+
+ case O (O_NOT, SB): /* not.b */
+ if (fetch2 (sd, &code->src, &rd))
+ goto end;
+ rd = ~rd;
+ v = 0;
+ goto shift8;
+
+ case O (O_NOT, SW): /* not.w */
+ if (fetch2 (sd, &code->src, &rd))
+ goto end;
+ rd = ~rd;
+ v = 0;
+ goto shift16;
+
+ case O (O_NOT, SL): /* not.l */
+ if (fetch2 (sd, &code->src, &rd))
+ goto end;
+ rd = ~rd;
+ v = 0;
+ goto shift32;
+
+ case O (O_SHLL, SB): /* shll.b */
+ case O (O_SHLR, SB): /* shlr.b */
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+
+ if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
+ ea = 1; /* unary op */
+ else /* binary op */
+ fetch (sd, &code->src, &ea);
+
+ if (code->opcode == O (O_SHLL, SB))
+ {
+ v = (ea > 8);
+ c = rd & (0x80 >> (ea - 1));
+ rd <<= ea;
+ }
+ else
+ {
+ v = 0;
+ c = rd & (1 << (ea - 1));
+ rd = (unsigned char) rd >> ea;
+ }
+ goto shift8;
+
+ case O (O_SHLL, SW): /* shll.w */
+ case O (O_SHLR, SW): /* shlr.w */
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+
+ if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
+ ea = 1; /* unary op */
+ else
+ fetch (sd, &code->src, &ea);
+
+ if (code->opcode == O (O_SHLL, SW))
+ {
+ v = (ea > 16);
+ c = rd & (0x8000 >> (ea - 1));
+ rd <<= ea;
+ }
+ else
+ {
+ v = 0;
+ c = rd & (1 << (ea - 1));
+ rd = (unsigned short) rd >> ea;
+ }
+ goto shift16;
+
+ case O (O_SHLL, SL): /* shll.l */
+ case O (O_SHLR, SL): /* shlr.l */
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+
+ if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
+ ea = 1; /* unary op */
+ else
+ fetch (sd, &code->src, &ea);
+
+ if (code->opcode == O (O_SHLL, SL))
+ {
+ v = (ea > 32);
+ c = rd & (0x80000000 >> (ea - 1));
+ rd <<= ea;
+ }
+ else
+ {
+ v = 0;
+ c = rd & (1 << (ea - 1));
+ rd = (unsigned int) rd >> ea;
+ }
+ goto shift32;
+
+ case O (O_SHAL, SB):
+ case O (O_SHAR, SB):
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+
+ if (code->src.type == X (OP_IMM, SB))
+ fetch (sd, &code->src, &ea);
+ else
+ ea = 1;
+
+ if (code->opcode == O (O_SHAL, SB))
+ {
+ c = rd & (0x80 >> (ea - 1));
+ res = rd >> (7 - ea);
+ v = ((res & 1) && !(res & 2))
+ || (!(res & 1) && (res & 2));
+ rd <<= ea;
+ }
+ else
+ {
+ c = rd & (1 << (ea - 1));
+ v = 0;
+ rd = ((signed char) rd) >> ea;
+ }
+ goto shift8;
+
+ case O (O_SHAL, SW):
+ case O (O_SHAR, SW):
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+
+ if (code->src.type == X (OP_IMM, SW))
+ fetch (sd, &code->src, &ea);
+ else
+ ea = 1;
+
+ if (code->opcode == O (O_SHAL, SW))
+ {
+ c = rd & (0x8000 >> (ea - 1));
+ res = rd >> (15 - ea);
+ v = ((res & 1) && !(res & 2))
+ || (!(res & 1) && (res & 2));
+ rd <<= ea;
+ }
+ else
+ {
+ c = rd & (1 << (ea - 1));
+ v = 0;
+ rd = ((signed short) rd) >> ea;
+ }
+ goto shift16;
+
+ case O (O_SHAL, SL):
+ case O (O_SHAR, SL):
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+
+ if (code->src.type == X (OP_IMM, SL))
+ fetch (sd, &code->src, &ea);
+ else
+ ea = 1;
+
+ if (code->opcode == O (O_SHAL, SL))
+ {
+ c = rd & (0x80000000 >> (ea - 1));
+ res = rd >> (31 - ea);
+ v = ((res & 1) && !(res & 2))
+ || (!(res & 1) && (res & 2));
+ rd <<= ea;
+ }
+ else
+ {
+ c = rd & (1 << (ea - 1));
+ v = 0;
+ rd = ((signed int) rd) >> ea;
+ }
+ goto shift32;
+
+ case O (O_ROTL, SB):
+ case O (O_ROTR, SB):
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+
+ if (code->src.type == X (OP_IMM, SB))
+ fetch (sd, &code->src, &ea);
+ else
+ ea = 1;
+
+ while (ea--)
+ if (code->opcode == O (O_ROTL, SB))
+ {
+ c = rd & 0x80;
+ rd <<= 1;
+ if (c)
+ rd |= 1;
+ }
+ else
+ {
+ c = rd & 1;
+ rd = ((unsigned char) rd) >> 1;
+ if (c)
+ rd |= 0x80;
+ }
+
+ v = 0;
+ goto shift8;
+
+ case O (O_ROTL, SW):
+ case O (O_ROTR, SW):
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+
+ if (code->src.type == X (OP_IMM, SW))
+ fetch (sd, &code->src, &ea);
+ else
+ ea = 1;
+
+ while (ea--)
+ if (code->opcode == O (O_ROTL, SW))
+ {
+ c = rd & 0x8000;
+ rd <<= 1;
+ if (c)
+ rd |= 1;
+ }
+ else
+ {
+ c = rd & 1;
+ rd = ((unsigned short) rd) >> 1;
+ if (c)
+ rd |= 0x8000;
+ }
+
+ v = 0;
+ goto shift16;
+
+ case O (O_ROTL, SL):
+ case O (O_ROTR, SL):
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+
+ if (code->src.type == X (OP_IMM, SL))
+ fetch (sd, &code->src, &ea);
+ else
+ ea = 1;
+
+ while (ea--)
+ if (code->opcode == O (O_ROTL, SL))
+ {
+ c = rd & 0x80000000;
+ rd <<= 1;
+ if (c)
+ rd |= 1;
+ }
+ else
+ {
+ c = rd & 1;
+ rd = ((unsigned int) rd) >> 1;
+ if (c)
+ rd |= 0x80000000;
+ }
+
+ v = 0;
+ goto shift32;
+
+ case O (O_ROTXL, SB):
+ case O (O_ROTXR, SB):
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+
+ if (code->src.type == X (OP_IMM, SB))
+ fetch (sd, &code->src, &ea);
+ else
+ ea = 1;
+
+ while (ea--)
+ if (code->opcode == O (O_ROTXL, SB))
+ {
+ res = rd & 0x80;
+ rd <<= 1;
+ if (C)
+ rd |= 1;
+ c = res;
+ }
+ else
+ {
+ res = rd & 1;
+ rd = ((unsigned char) rd) >> 1;
+ if (C)
+ rd |= 0x80;
+ c = res;
+ }
+
+ v = 0;
+ goto shift8;
+
+ case O (O_ROTXL, SW):
+ case O (O_ROTXR, SW):
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+
+ if (code->src.type == X (OP_IMM, SW))
+ fetch (sd, &code->src, &ea);
+ else
+ ea = 1;
+
+ while (ea--)
+ if (code->opcode == O (O_ROTXL, SW))
+ {
+ res = rd & 0x8000;
+ rd <<= 1;
+ if (C)
+ rd |= 1;
+ c = res;
+ }
+ else
+ {
+ res = rd & 1;
+ rd = ((unsigned short) rd) >> 1;
+ if (C)
+ rd |= 0x8000;
+ c = res;
+ }
+
+ v = 0;
+ goto shift16;
+
+ case O (O_ROTXL, SL):
+ case O (O_ROTXR, SL):
+ if (fetch2 (sd, &code->dst, &rd))
+ goto end;
+
+ if (code->src.type == X (OP_IMM, SL))
+ fetch (sd, &code->src, &ea);
+ else
+ ea = 1;
+
+ while (ea--)
+ if (code->opcode == O (O_ROTXL, SL))
+ {
+ res = rd & 0x80000000;
+ rd <<= 1;
+ if (C)
+ rd |= 1;
+ c = res;
+ }
+ else
+ {
+ res = rd & 1;
+ rd = ((unsigned int) rd) >> 1;
+ if (C)
+ rd |= 0x80000000;
+ c = res;
+ }
+
+ v = 0;
+ goto shift32;
+
+ case O (O_JMP, SN):
+ case O (O_JMP, SL):
+ case O (O_JMP, SB): /* jmp */
+ case O (O_JMP, SW):
+ fetch (sd, &code->src, &pc);
+ goto end;
+
+ case O (O_JSR, SN):
+ case O (O_JSR, SL):
+ case O (O_JSR, SB): /* jsr, jump to subroutine */
+ case O (O_JSR, SW):
+ if (fetch (sd, &code->src, &pc))
+ goto end;
+ call:
+ tmp = h8_get_reg (sd, SP_REGNUM);
+
+ if (h8300hmode && !h8300_normal_mode)
+ {
+ tmp -= 4;
+ SET_MEMORY_L (tmp, code->next_pc);
+ }
+ else
+ {
+ tmp -= 2;
+ SET_MEMORY_W (tmp, code->next_pc);
+ }
+ h8_set_reg (sd, SP_REGNUM, tmp);
+
+ goto end;
+
+ case O (O_BSR, SW):
+ case O (O_BSR, SL):
+ case O (O_BSR, SB): /* bsr, branch to subroutine */
+ if (fetch (sd, &code->src, &res))
+ goto end;
+ pc = code->next_pc + res;
+ goto call;
+
+ case O (O_RTE, SN): /* rte, return from exception */
+ rte:
+ /* Pops exr and ccr before pc -- otherwise identical to rts. */
+ tmp = h8_get_reg (sd, SP_REGNUM);
+
+ if (h8300smode) /* pop exr */
+ {
+ h8_set_exr (sd, GET_MEMORY_L (tmp));
+ tmp += 4;
+ }
+ if (h8300hmode && !h8300_normal_mode)
+ {
+ h8_set_ccr (sd, GET_MEMORY_L (tmp));
+ tmp += 4;
+ pc = GET_MEMORY_L (tmp);
+ tmp += 4;
+ }
+ else
+ {
+ h8_set_ccr (sd, GET_MEMORY_W (tmp));
+ tmp += 2;
+ pc = GET_MEMORY_W (tmp);
+ tmp += 2;
+ }
+
+ GETSR (sd);
+ h8_set_reg (sd, SP_REGNUM, tmp);
+ goto end;
+
+ case O (O_RTS, SN): /* rts, return from subroutine */
+ rts:
+ tmp = h8_get_reg (sd, SP_REGNUM);
+
+ if (h8300hmode && !h8300_normal_mode)
+ {
+ pc = GET_MEMORY_L (tmp);
+ tmp += 4;
+ }
+ else
+ {
+ pc = GET_MEMORY_W (tmp);
+ tmp += 2;
+ }