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[libreriscv.git]
/
simple_v_extension
/
simple_v_chennai_2018.tex
diff --git
a/simple_v_extension/simple_v_chennai_2018.tex
b/simple_v_extension/simple_v_chennai_2018.tex
index 14e593c435fe139abec15cf85de504baa461bdee..3e6e47d7cf86681ca0c66b4f955fab37ec6bf574 100644
(file)
--- a/
simple_v_extension/simple_v_chennai_2018.tex
+++ b/
simple_v_extension/simple_v_chennai_2018.tex
@@
-50,7
+50,7
@@
https://sigarch.org/simd-instructions-considered-harmful
\item Setup and corner-cases alone are extremely complex.\\
Hardware is easy, but software is hell.
https://sigarch.org/simd-instructions-considered-harmful
\item Setup and corner-cases alone are extremely complex.\\
Hardware is easy, but software is hell.
- \item O($N^{6}$) ISA opcode proliferation
!
\\
+ \item O($N^{6}$) ISA opcode proliferation
(1000s of instructions)
\\
opcode, elwidth, veclen, src1-src2-dest hi/lo
\end{itemize}
}
opcode, elwidth, veclen, src1-src2-dest hi/lo
\end{itemize}
}
@@
-59,6
+59,8
@@
\begin{itemize}
\item Effectively a variant of SIMD / SIMT (arbitrary length)\vspace{4pt}
\begin{itemize}
\item Effectively a variant of SIMD / SIMT (arbitrary length)\vspace{4pt}
+ \item Fascinatingly, despite being a SIMD-variant, RVV only has
+ O(N) opcode proliferation! (extremely well designed)
\item Extremely powerful (extensible to 256 registers)\vspace{4pt}
\item Supports polymorphism, several datatypes (inc. FP16)\vspace{4pt}
\item Requires a separate Register File (32 w/ext to 256)\vspace{4pt}
\item Extremely powerful (extensible to 256 registers)\vspace{4pt}
\item Supports polymorphism, several datatypes (inc. FP16)\vspace{4pt}
\item Requires a separate Register File (32 w/ext to 256)\vspace{4pt}
@@
-66,11
+68,9
@@
\end{itemize}
However...
\begin{itemize}
\end{itemize}
However...
\begin{itemize}
- \item 98 percent opcode duplication with rest of RV
(CLIP)
+ \item 98 percent opcode duplication with rest of RV
\item Extending RVV requires customisation not just of h/w:\\
gcc, binutils also need customisation (and maintenance)
\item Extending RVV requires customisation not just of h/w:\\
gcc, binutils also need customisation (and maintenance)
- \item Fascinatingly, despite being a SIMD-variant, RVV only has
- O(N) opcode proliferation! (extremely well designed)
\end{itemize}
}
\end{itemize}
}
@@
-103,7
+103,7
@@
\frame{\frametitle{What's the value of SV? Why adopt it even in non-V?}
\begin{itemize}
\frame{\frametitle{What's the value of SV? Why adopt it even in non-V?}
\begin{itemize}
- \item memcpy
becomes much smaller (higher bang-per-buck)
+ \item memcpy
has a much higher bang-per-buck ratio
\item context-switch (LOAD/STORE multiple): 1-2 instructions
\item Compressed instrs further reduces I-cache (etc.)
\item Reduced I-cache load (and less I-reads)
\item context-switch (LOAD/STORE multiple): 1-2 instructions
\item Compressed instrs further reduces I-cache (etc.)
\item Reduced I-cache load (and less I-reads)
@@
-150,7
+150,7
@@
\item Standard and future and custom opcodes now parallel\\
(crucially: with NO extra instructions needing to be added)
\end{itemize}
\item Standard and future and custom opcodes now parallel\\
(crucially: with NO extra instructions needing to be added)
\end{itemize}
- Note: EVERY
THING is parallelised:
+ Note: EVERY
scalar op now paralleliseable
\begin{itemize}
\item All LOAD/STORE (inc. Compressed, Int/FP versions)
\item All ALU ops (Int, FP, SIMD, DSP, everything)
\begin{itemize}
\item All LOAD/STORE (inc. Compressed, Int/FP versions)
\item All ALU ops (Int, FP, SIMD, DSP, everything)
@@
-370,9
+370,9
@@
for (i = 0; i < 16; i++) // 16 CSRs?
\begin{semiverbatim}
def get\_pred\_val(bool is\_fp\_op, int reg):
tb = int\_pred if is\_fp\_op else fp\_pred
\begin{semiverbatim}
def get\_pred\_val(bool is\_fp\_op, int reg):
tb = int\_pred if is\_fp\_op else fp\_pred
- if (!tb[reg].enabled):
- return ~0x0 // all ops enabled
- predidx
= tb[reg].predidx // redirection occurs HERE
+ if (!tb[reg].enabled):
return ~0x0 // all ops enabled
+ predidx = tb[reg].predidx // redirection occurs HERE
+ predidx
+= tb[reg].bank << 5 // 0 (1=rsvd)
predicate = intreg[predidx] // actual predicate HERE
if (tb[reg].inv):
predicate = ~predicate // invert ALL bits
predicate = intreg[predidx] // actual predicate HERE
if (tb[reg].inv):
predicate = ~predicate // invert ALL bits
@@
-471,10
+471,10
@@
def get\_pred\_val(bool is\_fp\_op, int reg):
\begin{semiverbatim}
function op\_add(rd, rs1, rs2) # add not VADD!
int i, id=0, irs1=0, irs2=0;
\begin{semiverbatim}
function op\_add(rd, rs1, rs2) # add not VADD!
int i, id=0, irs1=0, irs2=0;
+ predval = get\_pred\_val(FALSE, rd);
rd = int\_vec[rd ].isvector ? int\_vec[rd ].regidx : rd;
rs1 = int\_vec[rs1].isvector ? int\_vec[rs1].regidx : rs1;
rs2 = int\_vec[rs2].isvector ? int\_vec[rs2].regidx : rs2;
rd = int\_vec[rd ].isvector ? int\_vec[rd ].regidx : rd;
rs1 = int\_vec[rs1].isvector ? int\_vec[rs1].regidx : rs1;
rs2 = int\_vec[rs2].isvector ? int\_vec[rs2].regidx : rs2;
- predval = get\_pred\_val(FALSE, rd);
for (i = 0; i < VL; i++)
if (predval \& 1<<i) # predication uses intregs
ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
for (i = 0; i < VL; i++)
if (predval \& 1<<i) # predication uses intregs
ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
@@
-687,7
+687,7
@@
loop:
CSRvect1 = \{type: F, key: a3, val: a3, elwidth: dflt\}
CSRvect2 = \{type: F, key: a7, val: a7, elwidth: dflt\}
loop:
CSRvect1 = \{type: F, key: a3, val: a3, elwidth: dflt\}
CSRvect2 = \{type: F, key: a7, val: a7, elwidth: dflt\}
loop:
- setvl t0, a0, 4 # vl = t0 = min(min(
mvl, 4, n
))
+ setvl t0, a0, 4 # vl = t0 = min(min(
63, 4), a0
))
ld a3, a1 # load 4 registers a3-6 from x
slli t1, t0, 3 # t1 = vl * 8 (in bytes)
ld a7, a2 # load 4 registers a7-10 from y
ld a3, a1 # load 4 registers a3-6 from x
slli t1, t0, 3 # t1 = vl * 8 (in bytes)
ld a7, a2 # load 4 registers a7-10 from y