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add category descriptions
[libreriscv.git]
/
simple_v_extension
/
simple_v_chennai_2018.tex
diff --git
a/simple_v_extension/simple_v_chennai_2018.tex
b/simple_v_extension/simple_v_chennai_2018.tex
index 902f7cc22a4ca9583b362fa488bdd1fff3d17c54..3e6e47d7cf86681ca0c66b4f955fab37ec6bf574 100644
(file)
--- a/
simple_v_extension/simple_v_chennai_2018.tex
+++ b/
simple_v_extension/simple_v_chennai_2018.tex
@@
-103,7
+103,7
@@
\frame{\frametitle{What's the value of SV? Why adopt it even in non-V?}
\begin{itemize}
\frame{\frametitle{What's the value of SV? Why adopt it even in non-V?}
\begin{itemize}
- \item memcpy
becomes much smaller (higher bang-per-buck)
+ \item memcpy
has a much higher bang-per-buck ratio
\item context-switch (LOAD/STORE multiple): 1-2 instructions
\item Compressed instrs further reduces I-cache (etc.)
\item Reduced I-cache load (and less I-reads)
\item context-switch (LOAD/STORE multiple): 1-2 instructions
\item Compressed instrs further reduces I-cache (etc.)
\item Reduced I-cache load (and less I-reads)
@@
-471,10
+471,10
@@
def get\_pred\_val(bool is\_fp\_op, int reg):
\begin{semiverbatim}
function op\_add(rd, rs1, rs2) # add not VADD!
int i, id=0, irs1=0, irs2=0;
\begin{semiverbatim}
function op\_add(rd, rs1, rs2) # add not VADD!
int i, id=0, irs1=0, irs2=0;
+ predval = get\_pred\_val(FALSE, rd);
rd = int\_vec[rd ].isvector ? int\_vec[rd ].regidx : rd;
rs1 = int\_vec[rs1].isvector ? int\_vec[rs1].regidx : rs1;
rs2 = int\_vec[rs2].isvector ? int\_vec[rs2].regidx : rs2;
rd = int\_vec[rd ].isvector ? int\_vec[rd ].regidx : rd;
rs1 = int\_vec[rs1].isvector ? int\_vec[rs1].regidx : rs1;
rs2 = int\_vec[rs2].isvector ? int\_vec[rs2].regidx : rs2;
- predval = get\_pred\_val(FALSE, rd);
for (i = 0; i < VL; i++)
if (predval \& 1<<i) # predication uses intregs
ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
for (i = 0; i < VL; i++)
if (predval \& 1<<i) # predication uses intregs
ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
@@
-687,7
+687,7
@@
loop:
CSRvect1 = \{type: F, key: a3, val: a3, elwidth: dflt\}
CSRvect2 = \{type: F, key: a7, val: a7, elwidth: dflt\}
loop:
CSRvect1 = \{type: F, key: a3, val: a3, elwidth: dflt\}
CSRvect2 = \{type: F, key: a7, val: a7, elwidth: dflt\}
loop:
- setvl t0, a0, 4 # vl = t0 = min(min(
mvl, 4, n
))
+ setvl t0, a0, 4 # vl = t0 = min(min(
63, 4), a0
))
ld a3, a1 # load 4 registers a3-6 from x
slli t1, t0, 3 # t1 = vl * 8 (in bytes)
ld a7, a2 # load 4 registers a7-10 from y
ld a3, a1 # load 4 registers a3-6 from x
slli t1, t0, 3 # t1 = vl * 8 (in bytes)
ld a7, a2 # load 4 registers a7-10 from y