+ info->has_graphics = gfx.available_rings > 0;
+ info->num_rings[RING_GFX] = util_bitcount(gfx.available_rings);
+ info->num_rings[RING_COMPUTE] = util_bitcount(compute.available_rings);
+ info->num_rings[RING_DMA] = util_bitcount(dma.available_rings);
+ info->num_rings[RING_UVD] = util_bitcount(uvd.available_rings);
+ info->num_rings[RING_VCE] = util_bitcount(vce.available_rings);
+ info->num_rings[RING_UVD_ENC] = util_bitcount(uvd_enc.available_rings);
+ info->num_rings[RING_VCN_DEC] = util_bitcount(vcn_dec.available_rings);
+ info->num_rings[RING_VCN_ENC] = util_bitcount(vcn_enc.available_rings);
+ info->num_rings[RING_VCN_JPEG] = util_bitcount(vcn_jpeg.available_rings);
+
+ /* This is "align_mask" copied from the kernel, maximums of all IP versions. */
+ info->ib_pad_dw_mask[RING_GFX] = 0xff;
+ info->ib_pad_dw_mask[RING_COMPUTE] = 0xff;
+ info->ib_pad_dw_mask[RING_DMA] = 0xf;
+ info->ib_pad_dw_mask[RING_UVD] = 0xf;
+ info->ib_pad_dw_mask[RING_VCE] = 0x3f;
+ info->ib_pad_dw_mask[RING_UVD_ENC] = 0x3f;
+ info->ib_pad_dw_mask[RING_VCN_DEC] = 0xf;
+ info->ib_pad_dw_mask[RING_VCN_ENC] = 0x3f;
+ info->ib_pad_dw_mask[RING_VCN_JPEG] = 0xf;
+
+ /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
+ * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
+ * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
+ */
+ info->has_clear_state = info->chip_class >= GFX7;
+
+ info->has_distributed_tess = info->chip_class >= GFX10 ||
+ (info->chip_class >= GFX8 && info->max_se >= 2);
+
+ info->has_dcc_constant_encode = info->family == CHIP_RAVEN2 ||
+ info->family == CHIP_RENOIR ||
+ info->chip_class >= GFX10;
+
+ info->has_rbplus = info->family == CHIP_STONEY ||
+ info->chip_class >= GFX9;
+
+ /* Some chips have RB+ registers, but don't support RB+. Those must
+ * always disable it.
+ */
+ info->rbplus_allowed = info->has_rbplus &&
+ (info->family == CHIP_STONEY ||
+ info->family == CHIP_VEGA12 ||
+ info->family == CHIP_RAVEN ||
+ info->family == CHIP_RAVEN2 ||
+ info->family == CHIP_RENOIR ||
+ info->chip_class >= GFX10_3);
+
+ info->has_out_of_order_rast = info->chip_class >= GFX8 &&
+ info->chip_class <= GFX9 &&
+ info->max_se >= 2;
+
+ /* Whether chips support double rate packed math instructions. */
+ info->has_packed_math_16bit = info->chip_class >= GFX9;
+
+ /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
+ info->has_load_ctx_reg_pkt = info->chip_class >= GFX9 ||
+ (info->chip_class >= GFX8 &&
+ info->me_fw_feature >= 41);
+
+ info->cpdma_prefetch_writes_memory = info->chip_class <= GFX8;
+
+ info->has_gfx9_scissor_bug = info->family == CHIP_VEGA10 ||
+ info->family == CHIP_RAVEN;
+
+ info->has_tc_compat_zrange_bug = info->chip_class >= GFX8 &&
+ info->chip_class <= GFX9;
+
+ info->has_msaa_sample_loc_bug = (info->family >= CHIP_POLARIS10 &&
+ info->family <= CHIP_POLARIS12) ||
+ info->family == CHIP_VEGA10 ||
+ info->family == CHIP_RAVEN;
+
+ info->has_ls_vgpr_init_bug = info->family == CHIP_VEGA10 ||
+ info->family == CHIP_RAVEN;