+
+void ac_print_gpu_info(struct radeon_info *info)
+{
+ printf("Device info:\n");
+ printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
+ info->pci_domain, info->pci_bus,
+ info->pci_dev, info->pci_func);
+ printf(" pci_id = 0x%x\n", info->pci_id);
+ printf(" family = %i\n", info->family);
+ printf(" chip_class = %i\n", info->chip_class);
+ printf(" num_compute_rings = %u\n", info->num_compute_rings);
+ printf(" num_sdma_rings = %i\n", info->num_sdma_rings);
+ printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
+ printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
+
+ printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
+ printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
+
+ printf("Memory info:\n");
+ printf(" pte_fragment_size = %u\n", info->pte_fragment_size);
+ printf(" gart_page_size = %u\n", info->gart_page_size);
+ printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
+ printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
+ printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
+ printf(" gds_size = %u kB\n", info->gds_size / 1024);
+ printf(" gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
+ printf(" max_alloc_size = %i MB\n",
+ (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
+ printf(" min_alloc_size = %u\n", info->min_alloc_size);
+ printf(" address32_hi = %u\n", info->address32_hi);
+ printf(" has_dedicated_vram = %u\n", info->has_dedicated_vram);
+
+ printf("CP info:\n");
+ printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
+ printf(" ib_start_alignment = %u\n", info->ib_start_alignment);
+ printf(" me_fw_version = %i\n", info->me_fw_version);
+ printf(" me_fw_feature = %i\n", info->me_fw_feature);
+ printf(" pfp_fw_version = %i\n", info->pfp_fw_version);
+ printf(" pfp_fw_feature = %i\n", info->pfp_fw_feature);
+ printf(" ce_fw_version = %i\n", info->ce_fw_version);
+ printf(" ce_fw_feature = %i\n", info->ce_fw_feature);
+
+ printf("Multimedia info:\n");
+ printf(" has_hw_decode = %u\n", info->has_hw_decode);
+ printf(" uvd_enc_supported = %u\n", info->uvd_enc_supported);
+ printf(" uvd_fw_version = %u\n", info->uvd_fw_version);
+ printf(" vce_fw_version = %u\n", info->vce_fw_version);
+ printf(" vce_harvest_config = %i\n", info->vce_harvest_config);
+
+ printf("Kernel & winsys capabilities:\n");
+ printf(" drm = %i.%i.%i\n", info->drm_major,
+ info->drm_minor, info->drm_patchlevel);
+ printf(" has_userptr = %i\n", info->has_userptr);
+ printf(" has_syncobj = %u\n", info->has_syncobj);
+ printf(" has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
+ printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
+ printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
+ printf(" has_local_buffers = %u\n", info->has_local_buffers);
+ printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
+ printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
+ printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
+ printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
+ printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
+ printf(" has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
+ printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
+ printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
+ printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
+ printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
+ printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
+ printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
+ printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
+ printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
+
+ printf("Shader core info:\n");
+ printf(" max_shader_clock = %i\n", info->max_shader_clock);
+ printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
+ printf(" num_good_cu_per_sh = %i\n", info->num_good_cu_per_sh);
+ printf(" num_tcc_blocks = %i\n", info->num_tcc_blocks);
+ printf(" max_se = %i\n", info->max_se);
+ printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
+
+ printf("Render backend info:\n");
+ printf(" num_render_backends = %i\n", info->num_render_backends);
+ printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
+ printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
+ printf(" enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
+ printf(" max_alignment = %u\n", (unsigned)info->max_alignment);
+
+ printf("GB_ADDR_CONFIG:\n");
+ if (info->chip_class >= GFX9) {
+ printf(" num_pipes = %u\n",
+ 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
+ printf(" pipe_interleave_size = %u\n",
+ 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
+ printf(" max_compressed_frags = %u\n",
+ 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
+ printf(" bank_interleave_size = %u\n",
+ 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
+ printf(" num_banks = %u\n",
+ 1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
+ printf(" shader_engine_tile_size = %u\n",
+ 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
+ printf(" num_shader_engines = %u\n",
+ 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
+ printf(" num_gpus = %u (raw)\n",
+ G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
+ printf(" multi_gpu_tile_size = %u (raw)\n",
+ G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
+ printf(" num_rb_per_se = %u\n",
+ 1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
+ printf(" row_size = %u\n",
+ 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
+ printf(" num_lower_pipes = %u (raw)\n",
+ G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
+ printf(" se_enable = %u (raw)\n",
+ G_0098F8_SE_ENABLE(info->gb_addr_config));
+ } else {
+ printf(" num_pipes = %u\n",
+ 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
+ printf(" pipe_interleave_size = %u\n",
+ 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
+ printf(" bank_interleave_size = %u\n",
+ 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
+ printf(" num_shader_engines = %u\n",
+ 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
+ printf(" shader_engine_tile_size = %u\n",
+ 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
+ printf(" num_gpus = %u (raw)\n",
+ G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
+ printf(" multi_gpu_tile_size = %u (raw)\n",
+ G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
+ printf(" row_size = %u\n",
+ 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
+ printf(" num_lower_pipes = %u (raw)\n",
+ G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
+ }
+}
+
+int
+ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
+{
+ if (chip_class >= GFX9)
+ return -1;
+
+ switch (family) {
+ case CHIP_OLAND:
+ case CHIP_HAINAN:
+ case CHIP_KAVERI:
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
+ case CHIP_ICELAND:
+ case CHIP_CARRIZO:
+ case CHIP_STONEY:
+ return 16;
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ case CHIP_BONAIRE:
+ case CHIP_HAWAII:
+ case CHIP_TONGA:
+ case CHIP_FIJI:
+ case CHIP_POLARIS10:
+ case CHIP_POLARIS11:
+ case CHIP_POLARIS12:
+ case CHIP_VEGAM:
+ return 32;
+ default:
+ unreachable("Unknown GPU");
+ }
+}
+
+void
+ac_get_raster_config(struct radeon_info *info,
+ uint32_t *raster_config_p,
+ uint32_t *raster_config_1_p,
+ uint32_t *se_tile_repeat_p)
+{
+ unsigned raster_config, raster_config_1, se_tile_repeat;
+
+ switch (info->family) {
+ /* 1 SE / 1 RB */
+ case CHIP_HAINAN:
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
+ case CHIP_STONEY:
+ raster_config = 0x00000000;
+ raster_config_1 = 0x00000000;
+ break;
+ /* 1 SE / 4 RBs */
+ case CHIP_VERDE:
+ raster_config = 0x0000124a;
+ raster_config_1 = 0x00000000;
+ break;
+ /* 1 SE / 2 RBs (Oland is special) */
+ case CHIP_OLAND:
+ raster_config = 0x00000082;
+ raster_config_1 = 0x00000000;
+ break;
+ /* 1 SE / 2 RBs */
+ case CHIP_KAVERI:
+ case CHIP_ICELAND:
+ case CHIP_CARRIZO:
+ raster_config = 0x00000002;
+ raster_config_1 = 0x00000000;
+ break;
+ /* 2 SEs / 4 RBs */
+ case CHIP_BONAIRE:
+ case CHIP_POLARIS11:
+ case CHIP_POLARIS12:
+ raster_config = 0x16000012;
+ raster_config_1 = 0x00000000;
+ break;
+ /* 2 SEs / 8 RBs */
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ raster_config = 0x2a00126a;
+ raster_config_1 = 0x00000000;
+ break;
+ /* 4 SEs / 8 RBs */
+ case CHIP_TONGA:
+ case CHIP_POLARIS10:
+ raster_config = 0x16000012;
+ raster_config_1 = 0x0000002a;
+ break;
+ /* 4 SEs / 16 RBs */
+ case CHIP_HAWAII:
+ case CHIP_FIJI:
+ case CHIP_VEGAM:
+ raster_config = 0x3a00161a;
+ raster_config_1 = 0x0000002e;
+ break;
+ default:
+ fprintf(stderr,
+ "ac: Unknown GPU, using 0 for raster_config\n");
+ raster_config = 0x00000000;
+ raster_config_1 = 0x00000000;
+ break;
+ }
+
+ /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
+ * This decreases performance by up to 50% when the RB is the bottleneck.
+ */
+ if (info->family == CHIP_KAVERI && info->drm_major == 2)
+ raster_config = 0x00000000;
+
+ /* Fiji: Old kernels have incorrect tiling config. This decreases
+ * RB performance by 25%. (it disables 1 RB in the second packer)
+ */
+ if (info->family == CHIP_FIJI &&
+ info->cik_macrotile_mode_array[0] == 0x000000e8) {
+ raster_config = 0x16000012;
+ raster_config_1 = 0x0000002a;
+ }
+
+ unsigned se_width = 8 << G_028350_SE_XSEL_GFX6(raster_config);
+ unsigned se_height = 8 << G_028350_SE_YSEL_GFX6(raster_config);
+
+ /* I don't know how to calculate this, though this is probably a good guess. */
+ se_tile_repeat = MAX2(se_width, se_height) * info->max_se;
+
+ *raster_config_p = raster_config;
+ *raster_config_1_p = raster_config_1;
+ if (se_tile_repeat_p)
+ *se_tile_repeat_p = se_tile_repeat;
+}
+
+void
+ac_get_harvested_configs(struct radeon_info *info,
+ unsigned raster_config,
+ unsigned *cik_raster_config_1_p,
+ unsigned *raster_config_se)
+{
+ unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
+ unsigned num_se = MAX2(info->max_se, 1);
+ unsigned rb_mask = info->enabled_rb_mask;
+ unsigned num_rb = MIN2(info->num_render_backends, 16);
+ unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
+ unsigned rb_per_se = num_rb / num_se;
+ unsigned se_mask[4];
+ unsigned se;
+
+ se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
+ se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
+ se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
+ se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
+
+ assert(num_se == 1 || num_se == 2 || num_se == 4);
+ assert(sh_per_se == 1 || sh_per_se == 2);
+ assert(rb_per_pkr == 1 || rb_per_pkr == 2);
+
+
+ if (info->chip_class >= CIK) {
+ unsigned raster_config_1 = *cik_raster_config_1_p;
+ if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
+ (!se_mask[2] && !se_mask[3]))) {
+ raster_config_1 &= C_028354_SE_PAIR_MAP;
+
+ if (!se_mask[0] && !se_mask[1]) {
+ raster_config_1 |=
+ S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
+ } else {
+ raster_config_1 |=
+ S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
+ }
+ *cik_raster_config_1_p = raster_config_1;
+ }
+ }
+
+ for (se = 0; se < num_se; se++) {
+ unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
+ unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
+ int idx = (se / 2) * 2;
+
+ raster_config_se[se] = raster_config;
+ if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
+ raster_config_se[se] &= C_028350_SE_MAP;
+
+ if (!se_mask[idx]) {
+ raster_config_se[se] |=
+ S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
+ } else {
+ raster_config_se[se] |=
+ S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
+ }
+ }
+
+ pkr0_mask &= rb_mask;
+ pkr1_mask &= rb_mask;
+ if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
+ raster_config_se[se] &= C_028350_PKR_MAP;
+
+ if (!pkr0_mask) {
+ raster_config_se[se] |=
+ S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
+ } else {
+ raster_config_se[se] |=
+ S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
+ }
+ }
+
+ if (rb_per_se >= 2) {
+ unsigned rb0_mask = 1 << (se * rb_per_se);
+ unsigned rb1_mask = rb0_mask << 1;
+
+ rb0_mask &= rb_mask;
+ rb1_mask &= rb_mask;
+ if (!rb0_mask || !rb1_mask) {
+ raster_config_se[se] &= C_028350_RB_MAP_PKR0;
+
+ if (!rb0_mask) {
+ raster_config_se[se] |=
+ S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
+ } else {
+ raster_config_se[se] |=
+ S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
+ }
+ }
+
+ if (rb_per_se > 2) {
+ rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
+ rb1_mask = rb0_mask << 1;
+ rb0_mask &= rb_mask;
+ rb1_mask &= rb_mask;
+ if (!rb0_mask || !rb1_mask) {
+ raster_config_se[se] &= C_028350_RB_MAP_PKR1;
+
+ if (!rb0_mask) {
+ raster_config_se[se] |=
+ S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
+ } else {
+ raster_config_se[se] |=
+ S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
+ }
+ }
+ }
+ }
+ }
+}