+ ib_align = MAX2(ib_align, vcn_jpeg.ib_size_alignment);
+ /* GFX10 and maybe GFX9 need this alignment for cache coherency. */
+ if (info->chip_class >= GFX9)
+ ib_align = MAX2(ib_align, info->tcc_cache_line_size);
+ /* The kernel pads gfx and compute IBs to 256 dwords since:
+ * 66f3b2d527154bd258a57c8815004b5964aa1cf5
+ * Do the same.
+ */
+ ib_align = MAX2(ib_align, 1024);
+ info->ib_alignment = ib_align;
+
+ if ((info->drm_minor >= 31 &&
+ (info->family == CHIP_RAVEN ||
+ info->family == CHIP_RAVEN2 ||
+ info->family == CHIP_RENOIR)) ||
+ (info->drm_minor >= 34 &&
+ (info->family == CHIP_NAVI12 ||
+ info->family == CHIP_NAVI14)) ||
+ info->chip_class >= GFX10_3) {
+ if (info->num_render_backends == 1)
+ info->use_display_dcc_unaligned = true;
+ else
+ info->use_display_dcc_with_retile_blit = true;
+ }
+
+ info->has_gds_ordered_append = info->chip_class >= GFX7 &&
+ info->drm_minor >= 29;
+
+ if (info->chip_class >= GFX9) {
+ unsigned pc_lines = 0;
+
+ switch (info->family) {
+ case CHIP_VEGA10:
+ case CHIP_VEGA12:
+ case CHIP_VEGA20:
+ pc_lines = 2048;
+ break;
+ case CHIP_RAVEN:
+ case CHIP_RAVEN2:
+ case CHIP_RENOIR:
+ case CHIP_NAVI10:
+ case CHIP_NAVI12:
+ case CHIP_SIENNA_CICHLID:
+ case CHIP_NAVY_FLOUNDER:
+ pc_lines = 1024;
+ break;
+ case CHIP_NAVI14:
+ pc_lines = 512;
+ break;
+ case CHIP_ARCTURUS:
+ break;
+ default:
+ assert(0);
+ }
+
+ info->pc_lines = pc_lines;
+
+ if (info->chip_class >= GFX10) {
+ info->pbb_max_alloc_count = pc_lines / 3;
+ } else {
+ info->pbb_max_alloc_count =
+ MIN2(128, pc_lines / (4 * info->max_se));
+ }
+ }
+
+ /* The number of SDPs is the same as the number of TCCs for now. */
+ if (info->chip_class >= GFX10)
+ info->num_sdp_interfaces = device_info.num_tcc_blocks;
+
+ if (info->chip_class >= GFX10_3)
+ info->max_wave64_per_simd = 16;
+ else if (info->chip_class == GFX10)
+ info->max_wave64_per_simd = 20;
+ else if (info->family >= CHIP_POLARIS10 && info->family <= CHIP_VEGAM)
+ info->max_wave64_per_simd = 8;
+ else
+ info->max_wave64_per_simd = 10;
+
+ if (info->chip_class >= GFX10) {
+ info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd;
+ info->min_sgpr_alloc = 128;
+ info->sgpr_alloc_granularity = 128;
+ /* Don't use late alloc on small chips. */
+ info->use_late_alloc = info->num_render_backends > 4;
+ } else if (info->chip_class >= GFX8) {
+ info->num_physical_sgprs_per_simd = 800;
+ info->min_sgpr_alloc = 16;
+ info->sgpr_alloc_granularity = 16;
+ info->use_late_alloc = true;
+ } else {
+ info->num_physical_sgprs_per_simd = 512;
+ info->min_sgpr_alloc = 8;
+ info->sgpr_alloc_granularity = 8;
+ /* Potential hang on Kabini: */
+ info->use_late_alloc = info->family != CHIP_KABINI;
+ }
+
+ info->max_sgpr_alloc = info->family == CHIP_TONGA ||
+ info->family == CHIP_ICELAND ? 96 : 104;
+
+ info->min_wave64_vgpr_alloc = 4;
+ info->max_vgpr_alloc = 256;
+ info->wave64_vgpr_alloc_granularity = 4;
+
+ info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256;
+ info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4;