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amd/common: add chip_class to ac_llvm_context
[mesa.git]
/
src
/
amd
/
common
/
ac_gpu_info.h
diff --git
a/src/amd/common/ac_gpu_info.h
b/src/amd/common/ac_gpu_info.h
index 9bf2b84d85183ea4aec9a5d8d9f04976c5d1521b..5722709d24f97ac952fa70001f6f655030a6e4bc 100644
(file)
--- a/
src/amd/common/ac_gpu_info.h
+++ b/
src/amd/common/ac_gpu_info.h
@@
-26,9
+26,18
@@
#ifndef AC_GPU_INFO_H
#define AC_GPU_INFO_H
#ifndef AC_GPU_INFO_H
#define AC_GPU_INFO_H
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
#include "amd_family.h"
#include "amd_family.h"
-#include <amdgpu.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Prior to C11 the following may trigger a typedef redeclaration warning */
+typedef struct amdgpu_device *amdgpu_device_handle;
+struct amdgpu_gpu_info;
struct radeon_info {
/* PCI info: domain:bus:dev:func */
struct radeon_info {
/* PCI info: domain:bus:dev:func */
@@
-41,6
+50,7
@@
struct radeon_info {
uint32_t pci_id;
enum radeon_family family;
enum chip_class chip_class;
uint32_t pci_id;
enum radeon_family family;
enum chip_class chip_class;
+ uint32_t pte_fragment_size;
uint32_t gart_page_size;
uint64_t gart_size;
uint64_t vram_size;
uint32_t gart_page_size;
uint64_t gart_size;
uint64_t vram_size;
@@
-50,14
+60,17
@@
struct radeon_info {
bool has_dedicated_vram;
bool has_virtual_memory;
bool gfx_ib_pad_with_type2;
bool has_dedicated_vram;
bool has_virtual_memory;
bool gfx_ib_pad_with_type2;
- bool has_
uvd
;
+ bool has_
hw_decode
;
uint32_t num_sdma_rings;
uint32_t num_compute_rings;
uint32_t uvd_fw_version;
uint32_t vce_fw_version;
uint32_t me_fw_version;
uint32_t num_sdma_rings;
uint32_t num_compute_rings;
uint32_t uvd_fw_version;
uint32_t vce_fw_version;
uint32_t me_fw_version;
+ uint32_t me_fw_feature;
uint32_t pfp_fw_version;
uint32_t pfp_fw_version;
+ uint32_t pfp_fw_feature;
uint32_t ce_fw_version;
uint32_t ce_fw_version;
+ uint32_t ce_fw_feature;
uint32_t vce_harvest_config;
uint32_t clock_crystal_freq;
uint32_t tcc_cache_line_size;
uint32_t vce_harvest_config;
uint32_t clock_crystal_freq;
uint32_t tcc_cache_line_size;
@@
-67,6
+80,7
@@
struct radeon_info {
uint32_t drm_minor;
uint32_t drm_patchlevel;
bool has_userptr;
uint32_t drm_minor;
uint32_t drm_patchlevel;
bool has_userptr;
+ bool has_syncobj;
/* Shader cores. */
uint32_t r600_max_quad_pipes; /* wave size / 16 */
/* Shader cores. */
uint32_t r600_max_quad_pipes; /* wave size / 16 */
@@
-86,6
+100,7
@@
struct radeon_info {
uint32_t pipe_interleave_bytes;
uint32_t enabled_rb_mask; /* GCN harvest config */
uint32_t pipe_interleave_bytes;
uint32_t enabled_rb_mask; /* GCN harvest config */
+ uint64_t max_alignment; /* from addrlib */
/* Tile modes. */
uint32_t si_tile_mode_array[32];
uint32_t cik_macrotile_mode_array[16];
/* Tile modes. */
uint32_t si_tile_mode_array[32];
uint32_t cik_macrotile_mode_array[16];
@@
-95,4
+110,12
@@
bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
struct radeon_info *info,
struct amdgpu_gpu_info *amdinfo);
struct radeon_info *info,
struct amdgpu_gpu_info *amdinfo);
+void ac_compute_driver_uuid(char *uuid, size_t size);
+
+void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
#endif /* AC_GPU_INFO_H */
#endif /* AC_GPU_INFO_H */