-union ac_shader_variant_key {
- struct ac_vs_variant_key vs;
- struct ac_fs_variant_key fs;
- struct ac_tes_variant_key tes;
- struct ac_tcs_variant_key tcs;
-};
-
-struct ac_nir_compiler_options {
- struct radv_pipeline_layout *layout;
- union ac_shader_variant_key key;
- bool unsafe_math;
- bool supports_spill;
- enum radeon_family family;
- enum chip_class chip_class;
-};
-
-struct ac_userdata_info {
- int8_t sgpr_idx;
- uint8_t num_sgprs;
- bool indirect;
- uint32_t indirect_offset;
-};
-
-enum ac_ud_index {
- AC_UD_SCRATCH_RING_OFFSETS = 0,
- AC_UD_PUSH_CONSTANTS = 1,
- AC_UD_INDIRECT_DESCRIPTOR_SETS = 2,
- AC_UD_SHADER_START = 3,
- AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
- AC_UD_VS_BASE_VERTEX_START_INSTANCE,
- AC_UD_VS_LS_TCS_IN_LAYOUT,
- AC_UD_VS_MAX_UD,
- AC_UD_PS_SAMPLE_POS_OFFSET = AC_UD_SHADER_START,
- AC_UD_PS_MAX_UD,
- AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
- AC_UD_CS_MAX_UD,
- AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_SHADER_START,
- AC_UD_GS_MAX_UD,
- AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
- AC_UD_TCS_MAX_UD,
- AC_UD_TES_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
- AC_UD_TES_MAX_UD,
- AC_UD_MAX_UD = AC_UD_VS_MAX_UD,
-};
-
-/* descriptor index into scratch ring offsets */
-#define RING_SCRATCH 0
-#define RING_ESGS_VS 1
-#define RING_ESGS_GS 2
-#define RING_GSVS_VS 3
-#define RING_GSVS_GS 4
-#define RING_HS_TESS_FACTOR 5
-#define RING_HS_TESS_OFFCHIP 6
-#define RING_PS_SAMPLE_POSITIONS 7
-
-// Match MAX_SETS from radv_descriptor_set.h
-#define AC_UD_MAX_SETS MAX_SETS