+struct NOP_ctx_gfx6 {
+ void join(const NOP_ctx_gfx6 &other) {
+ set_vskip_mode_then_vector = MAX2(set_vskip_mode_then_vector, other.set_vskip_mode_then_vector);
+ valu_wr_vcc_then_vccz = MAX2(valu_wr_vcc_then_vccz, other.valu_wr_vcc_then_vccz);
+ valu_wr_exec_then_execz = MAX2(valu_wr_exec_then_execz, other.valu_wr_exec_then_execz);
+ valu_wr_vcc_then_div_fmas = MAX2(valu_wr_vcc_then_div_fmas, other.valu_wr_vcc_then_div_fmas);
+ salu_wr_m0_then_gds_msg_ttrace = MAX2(salu_wr_m0_then_gds_msg_ttrace, other.salu_wr_m0_then_gds_msg_ttrace);
+ valu_wr_exec_then_dpp = MAX2(valu_wr_exec_then_dpp, other.valu_wr_exec_then_dpp);
+ salu_wr_m0_then_lds = MAX2(salu_wr_m0_then_lds, other.salu_wr_m0_then_lds);
+ salu_wr_m0_then_moverel = MAX2(salu_wr_m0_then_moverel, other.salu_wr_m0_then_moverel);
+ setreg_then_getsetreg = MAX2(setreg_then_getsetreg, other.setreg_then_getsetreg);
+ vmem_store_then_wr_data |= other.vmem_store_then_wr_data;
+ smem_clause |= other.smem_clause;
+ smem_write |= other.smem_write;
+ for (unsigned i = 0; i < BITSET_WORDS(128); i++) {
+ smem_clause_read_write[i] |= other.smem_clause_read_write[i];
+ smem_clause_write[i] |= other.smem_clause_write[i];
+ }
+ }
+
+ bool operator==(const NOP_ctx_gfx6 &other)
+ {
+ return
+ set_vskip_mode_then_vector == other.set_vskip_mode_then_vector &&
+ valu_wr_vcc_then_vccz == other.valu_wr_vcc_then_vccz &&
+ valu_wr_exec_then_execz == other.valu_wr_exec_then_execz &&
+ valu_wr_vcc_then_div_fmas == other.valu_wr_vcc_then_div_fmas &&
+ vmem_store_then_wr_data == other.vmem_store_then_wr_data &&
+ salu_wr_m0_then_gds_msg_ttrace == other.salu_wr_m0_then_gds_msg_ttrace &&
+ valu_wr_exec_then_dpp == other.valu_wr_exec_then_dpp &&
+ salu_wr_m0_then_lds == other.salu_wr_m0_then_lds &&
+ salu_wr_m0_then_moverel == other.salu_wr_m0_then_moverel &&
+ setreg_then_getsetreg == other.setreg_then_getsetreg &&
+ smem_clause == other.smem_clause &&
+ smem_write == other.smem_write &&
+ BITSET_EQUAL(smem_clause_read_write, other.smem_clause_read_write) &&
+ BITSET_EQUAL(smem_clause_write, other.smem_clause_write);
+ }
+
+ void add_wait_states(unsigned amount)
+ {
+ if ((set_vskip_mode_then_vector -= amount) < 0)
+ set_vskip_mode_then_vector = 0;
+
+ if ((valu_wr_vcc_then_vccz -= amount) < 0)
+ valu_wr_vcc_then_vccz = 0;
+
+ if ((valu_wr_exec_then_execz -= amount) < 0)
+ valu_wr_exec_then_execz = 0;
+
+ if ((valu_wr_vcc_then_div_fmas -= amount) < 0)
+ valu_wr_vcc_then_div_fmas = 0;
+
+ if ((salu_wr_m0_then_gds_msg_ttrace -= amount) < 0)
+ salu_wr_m0_then_gds_msg_ttrace = 0;
+
+ if ((valu_wr_exec_then_dpp -= amount) < 0)
+ valu_wr_exec_then_dpp = 0;
+
+ if ((salu_wr_m0_then_lds -= amount) < 0)
+ salu_wr_m0_then_lds = 0;
+
+ if ((salu_wr_m0_then_moverel -= amount) < 0)
+ salu_wr_m0_then_moverel = 0;
+
+ if ((setreg_then_getsetreg -= amount) < 0)
+ setreg_then_getsetreg = 0;
+
+ vmem_store_then_wr_data.reset();
+ }
+
+ /* setting MODE.vskip and then any vector op requires 2 wait states */
+ int8_t set_vskip_mode_then_vector = 0;
+
+ /* VALU writing VCC/EXEC and then a VALU reading VCCZ/EXECZ requires 5 wait states */
+ int8_t valu_wr_vcc_then_vccz = 0;
+ int8_t valu_wr_exec_then_execz = 0;
+
+ /* VALU writing VCC followed by v_div_fmas require 4 wait states */
+ int8_t valu_wr_vcc_then_div_fmas = 0;