- radv_cs_add_buffer(ws, cs, shader->bo, 8);
- radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
-}
-
-static void
-radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
- struct radv_pipeline *pipeline)
-{
- radv_emit_shader_prefetch(cmd_buffer,
- pipeline->shaders[MESA_SHADER_VERTEX]);
- radv_emit_VBO_descriptors_prefetch(cmd_buffer);
- radv_emit_shader_prefetch(cmd_buffer,
- pipeline->shaders[MESA_SHADER_TESS_CTRL]);
- radv_emit_shader_prefetch(cmd_buffer,
- pipeline->shaders[MESA_SHADER_TESS_EVAL]);
- radv_emit_shader_prefetch(cmd_buffer,
- pipeline->shaders[MESA_SHADER_GEOMETRY]);
- radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
- radv_emit_shader_prefetch(cmd_buffer,
- pipeline->shaders[MESA_SHADER_FRAGMENT]);
-}
-
-static void
-radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
- struct radv_pipeline *pipeline,
- struct radv_shader_variant *shader)
-{
- uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
-
- radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
- pipeline->graphics.vs.spi_vs_out_config);
-
- radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
- pipeline->graphics.vs.spi_shader_pos_format);
-
- radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
- radeon_emit(cmd_buffer->cs, va >> 8);
- radeon_emit(cmd_buffer->cs, va >> 40);
- radeon_emit(cmd_buffer->cs, shader->rsrc1);
- radeon_emit(cmd_buffer->cs, shader->rsrc2);
-
- radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
- S_028818_VTX_W0_FMT(1) |
- S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
- S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
- S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
-
-
- radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
- pipeline->graphics.vs.pa_cl_vs_out_cntl);
-
- if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
- radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
- pipeline->graphics.vs.vgt_reuse_off);
-}
-
-static void
-radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
- struct radv_pipeline *pipeline,
- struct radv_shader_variant *shader)
-{
- uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
-
- radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
- radeon_emit(cmd_buffer->cs, va >> 8);
- radeon_emit(cmd_buffer->cs, va >> 40);
- radeon_emit(cmd_buffer->cs, shader->rsrc1);
- radeon_emit(cmd_buffer->cs, shader->rsrc2);