+ uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
+
+ radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
+ radeon_emit(cmd_buffer->cs, gsvs_itemsize);
+ radeon_emit(cmd_buffer->cs, gsvs_itemsize);
+ radeon_emit(cmd_buffer->cs, gsvs_itemsize);
+
+ radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
+
+ radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
+
+ uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
+ radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
+ radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
+ radeon_emit(cmd_buffer->cs, 0);
+ radeon_emit(cmd_buffer->cs, 0);
+ radeon_emit(cmd_buffer->cs, 0);
+
+ uint32_t gs_num_invocations = gs->info.gs.invocations;
+ radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
+ S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
+ S_028B90_ENABLE(gs_num_invocations > 0));
+
+ va = ws->buffer_get_va(gs->bo);
+ ws->cs_add_buffer(cmd_buffer->cs, gs->bo, 8);
+ radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
+ radeon_emit(cmd_buffer->cs, va >> 8);
+ radeon_emit(cmd_buffer->cs, va >> 40);
+ radeon_emit(cmd_buffer->cs, gs->rsrc1);
+ radeon_emit(cmd_buffer->cs, gs->rsrc2);
+
+ radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
+
+ struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
+ AC_UD_GS_VS_RING_STRIDE_ENTRIES);
+ if (loc->sgpr_idx != -1) {
+ uint32_t stride = gs->info.gs.max_gsvs_emit_size;
+ uint32_t num_entries = 64;
+ bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
+
+ if (is_vi)
+ num_entries *= stride;
+
+ stride = S_008F04_STRIDE(stride);
+ radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
+ radeon_emit(cmd_buffer->cs, stride);
+ radeon_emit(cmd_buffer->cs, num_entries);
+ }
+}