- uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
-
- radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
- pipeline->graphics.vs.spi_vs_out_config);
-
- radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
- pipeline->graphics.vs.spi_shader_pos_format);
-
- radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
- radeon_emit(cmd_buffer->cs, va >> 8);
- radeon_emit(cmd_buffer->cs, va >> 40);
- radeon_emit(cmd_buffer->cs, shader->rsrc1);
- radeon_emit(cmd_buffer->cs, shader->rsrc2);
-
- radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
- S_028818_VTX_W0_FMT(1) |
- S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
- S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
- S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
-
-
- radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
- pipeline->graphics.vs.pa_cl_vs_out_cntl);
-
- if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
- radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
- pipeline->graphics.vs.vgt_reuse_off);
-}
-
-static void
-radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
- struct radv_pipeline *pipeline,
- struct radv_shader_variant *shader)
-{
- uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
-
- radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
- radeon_emit(cmd_buffer->cs, va >> 8);
- radeon_emit(cmd_buffer->cs, va >> 40);
- radeon_emit(cmd_buffer->cs, shader->rsrc1);
- radeon_emit(cmd_buffer->cs, shader->rsrc2);
-}
-
-static void
-radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
- struct radv_shader_variant *shader)
-{
- uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
- uint32_t rsrc2 = shader->rsrc2;
-
- radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
- radeon_emit(cmd_buffer->cs, va >> 8);
- radeon_emit(cmd_buffer->cs, va >> 40);
-
- rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
- if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
- cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
- radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
-
- radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
- radeon_emit(cmd_buffer->cs, shader->rsrc1);
- radeon_emit(cmd_buffer->cs, rsrc2);
-}
-
-static void
-radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
- struct radv_shader_variant *shader)
-{
- uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
-
- if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
- radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
- radeon_emit(cmd_buffer->cs, va >> 8);
- radeon_emit(cmd_buffer->cs, va >> 40);
-
- radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
- radeon_emit(cmd_buffer->cs, shader->rsrc1);
- radeon_emit(cmd_buffer->cs, shader->rsrc2 |
- S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
- } else {
- radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
- radeon_emit(cmd_buffer->cs, va >> 8);
- radeon_emit(cmd_buffer->cs, va >> 40);
- radeon_emit(cmd_buffer->cs, shader->rsrc1);
- radeon_emit(cmd_buffer->cs, shader->rsrc2);
- }
-}
-
-static void
-radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
- struct radv_pipeline *pipeline)
-{
- struct radv_shader_variant *vs;
-
- radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
-
- /* Skip shaders merged into HS/GS */
- vs = pipeline->shaders[MESA_SHADER_VERTEX];
- if (!vs)
- return;
-
- if (vs->info.vs.as_ls)
- radv_emit_hw_ls(cmd_buffer, vs);
- else if (vs->info.vs.as_es)
- radv_emit_hw_es(cmd_buffer, pipeline, vs);
- else
- radv_emit_hw_vs(cmd_buffer, pipeline, vs);
-}
-
-
-static void
-radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
- struct radv_pipeline *pipeline)
-{
- if (!radv_pipeline_has_tess(pipeline))
- return;
-
- struct radv_shader_variant *tes, *tcs;
-
- tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
- tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];