+static void
+radv_image_view_make_descriptor(struct radv_image_view *iview,
+ struct radv_device *device,
+ const VkComponentMapping *components,
+ bool is_storage_image)
+{
+ struct radv_image *image = iview->image;
+ bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
+ uint32_t blk_w;
+ uint32_t *descriptor;
+ uint32_t hw_level = 0;
+
+ if (is_storage_image) {
+ descriptor = iview->storage_descriptor;
+ } else {
+ descriptor = iview->descriptor;
+ }
+
+ assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
+ blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
+
+ if (device->physical_device->rad_info.chip_class >= GFX9)
+ hw_level = iview->base_mip;
+ si_make_texture_descriptor(device, image, is_storage_image,
+ iview->type,
+ iview->vk_format,
+ components,
+ hw_level, hw_level + iview->level_count - 1,
+ iview->base_layer,
+ iview->base_layer + iview->layer_count - 1,
+ iview->extent.width,
+ iview->extent.height,
+ iview->extent.depth,
+ descriptor,
+ descriptor + 8);
+
+ const struct legacy_surf_level *base_level_info = NULL;
+ if (device->physical_device->rad_info.chip_class <= GFX9) {
+ if (is_stencil)
+ base_level_info = &image->surface.u.legacy.stencil_level[iview->base_mip];
+ else
+ base_level_info = &image->surface.u.legacy.level[iview->base_mip];
+ }
+ si_set_mutable_tex_desc_fields(device, image,
+ base_level_info,
+ iview->base_mip,
+ iview->base_mip,
+ blk_w, is_stencil, descriptor);
+}
+