+
+static bool
+radv_use_tc_compat_htile_for_image(struct radv_device *device,
+ const VkImageCreateInfo *pCreateInfo)
+{
+ /* TC-compat HTILE is only available for GFX8+. */
+ if (device->physical_device->rad_info.chip_class < GFX8)
+ return false;
+
+ if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
+ (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
+ return false;
+
+ if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
+ return false;
+
+ if (pCreateInfo->mipLevels > 1)
+ return false;
+
+ /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
+ * tests - disable for now. On GFX10 D32_SFLOAT is affected as well.
+ */
+ if (pCreateInfo->samples >= 2 &&
+ (pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
+ (pCreateInfo->format == VK_FORMAT_D32_SFLOAT &&
+ device->physical_device->rad_info.chip_class == GFX10)))
+ return false;
+
+ /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
+ * supports 32-bit. Though, it's possible to enable TC-compat for
+ * 16-bit depth surfaces if no Z planes are compressed.
+ */
+ if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
+ pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
+ pCreateInfo->format != VK_FORMAT_D16_UNORM)
+ return false;
+
+ if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
+ const struct VkImageFormatListCreateInfoKHR *format_list =
+ (const struct VkImageFormatListCreateInfoKHR *)
+ vk_find_struct_const(pCreateInfo->pNext,
+ IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
+
+ /* We have to ignore the existence of the list if viewFormatCount = 0 */
+ if (format_list && format_list->viewFormatCount) {
+ /* compatibility is transitive, so we only need to check
+ * one format with everything else.
+ */
+ for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
+ if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
+ continue;
+
+ if (pCreateInfo->format != format_list->pViewFormats[i])
+ return false;
+ }
+ } else {
+ return false;
+ }
+ }
+
+ return true;
+}
+
+static bool
+radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
+{
+ if (info->scanout)
+ return true;
+
+ if (!info->bo_metadata)
+ return false;
+
+ if (device->physical_device->rad_info.chip_class >= GFX9) {
+ return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
+ } else {
+ return info->bo_metadata->u.legacy.scanout;
+ }
+}
+
+static bool
+radv_use_dcc_for_image(struct radv_device *device,
+ const struct radv_image *image,
+ const struct radv_image_create_info *create_info,
+ const VkImageCreateInfo *pCreateInfo)
+{
+ bool dcc_compatible_formats;
+ bool blendable;
+
+ /* DCC (Delta Color Compression) is only available for GFX8+. */
+ if (device->physical_device->rad_info.chip_class < GFX8)
+ return false;
+
+ if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
+ return false;
+
+ if (image->shareable)
+ return false;
+
+ /* TODO: Enable DCC for storage images. */
+ if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
+ (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
+ return false;
+
+ if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
+ return false;
+
+ if (vk_format_is_subsampled(pCreateInfo->format) ||
+ vk_format_get_plane_count(pCreateInfo->format) > 1)
+ return false;
+
+ /* TODO: Enable DCC for mipmaps on GFX9+. */
+ if ((pCreateInfo->arrayLayers > 1 || pCreateInfo->mipLevels > 1) &&
+ device->physical_device->rad_info.chip_class >= GFX9)
+ return false;
+
+ /* Do not enable DCC for mipmapped arrays because performance is worse. */
+ if (pCreateInfo->arrayLayers > 1 && pCreateInfo->mipLevels > 1)
+ return false;
+
+ if (radv_surface_has_scanout(device, create_info))
+ return false;
+
+ /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
+ * 2x can be enabled with an option.
+ */
+ if (pCreateInfo->samples > 2 ||
+ (pCreateInfo->samples == 2 &&
+ !device->physical_device->dcc_msaa_allowed))
+ return false;
+
+ /* Determine if the formats are DCC compatible. */
+ dcc_compatible_formats =
+ radv_is_colorbuffer_format_supported(pCreateInfo->format,
+ &blendable);
+
+ if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
+ const struct VkImageFormatListCreateInfoKHR *format_list =
+ (const struct VkImageFormatListCreateInfoKHR *)
+ vk_find_struct_const(pCreateInfo->pNext,
+ IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
+
+ /* We have to ignore the existence of the list if viewFormatCount = 0 */
+ if (format_list && format_list->viewFormatCount) {
+ /* compatibility is transitive, so we only need to check
+ * one format with everything else. */
+ for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
+ if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
+ continue;
+
+ if (!radv_dcc_formats_compatible(pCreateInfo->format,
+ format_list->pViewFormats[i]))
+ dcc_compatible_formats = false;
+ }
+ } else {
+ dcc_compatible_formats = false;
+ }
+ }
+
+ if (!dcc_compatible_formats)
+ return false;
+
+ return true;
+}
+
+static bool
+radv_use_tc_compat_cmask_for_image(struct radv_device *device,
+ struct radv_image *image)
+{
+ if (!(device->instance->perftest_flags & RADV_PERFTEST_TC_COMPAT_CMASK))
+ return false;
+
+ /* TC-compat CMASK is only available for GFX8+. */
+ if (device->physical_device->rad_info.chip_class < GFX8)
+ return false;
+
+ if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
+ return false;
+
+ if (radv_image_has_dcc(image))
+ return false;
+
+ if (!radv_image_has_cmask(image))
+ return false;
+
+ return true;
+}
+
+static void
+radv_prefill_surface_from_metadata(struct radv_device *device,
+ struct radeon_surf *surface,
+ const struct radv_image_create_info *create_info)
+{
+ const struct radeon_bo_metadata *md = create_info->bo_metadata;
+ if (device->physical_device->rad_info.chip_class >= GFX9) {
+ if (md->u.gfx9.swizzle_mode > 0)
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+ else
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
+
+ surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode;
+ } else {
+ surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
+ surface->u.legacy.bankw = md->u.legacy.bankw;
+ surface->u.legacy.bankh = md->u.legacy.bankh;
+ surface->u.legacy.tile_split = md->u.legacy.tile_split;
+ surface->u.legacy.mtilea = md->u.legacy.mtilea;
+ surface->u.legacy.num_banks = md->u.legacy.num_banks;
+
+ if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+ else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
+ else
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
+
+ }
+}
+