+ VkDescriptorSetLayoutCreateInfo ds_create_info = {
+ .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
+ .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
+ .bindingCount = 2,
+ .pBindings = (VkDescriptorSetLayoutBinding[]) {
+ {
+ .binding = 0,
+ .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
+ .descriptorCount = 1,
+ .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
+ .pImmutableSamplers = NULL
+ },
+ {
+ .binding = 1,
+ .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
+ .descriptorCount = 1,
+ .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
+ .pImmutableSamplers = NULL
+ },
+ }
+ };
+
+ result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
+ &ds_create_info,
+ &device->meta_state.alloc,
+ &device->meta_state.itoi_r32g32b32.img_ds_layout);
+ if (result != VK_SUCCESS)
+ goto fail;
+
+
+ VkPipelineLayoutCreateInfo pl_create_info = {
+ .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
+ .setLayoutCount = 1,
+ .pSetLayouts = &device->meta_state.itoi_r32g32b32.img_ds_layout,
+ .pushConstantRangeCount = 1,
+ .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 24},
+ };
+
+ result = radv_CreatePipelineLayout(radv_device_to_handle(device),
+ &pl_create_info,
+ &device->meta_state.alloc,
+ &device->meta_state.itoi_r32g32b32.img_p_layout);
+ if (result != VK_SUCCESS)
+ goto fail;
+
+ /* compute shader */
+
+ VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
+ .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
+ .stage = VK_SHADER_STAGE_COMPUTE_BIT,
+ .module = radv_shader_module_to_handle(&cs),
+ .pName = "main",
+ .pSpecializationInfo = NULL,
+ };
+
+ VkComputePipelineCreateInfo vk_pipeline_info = {
+ .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
+ .stage = pipeline_shader_stage,
+ .flags = 0,
+ .layout = device->meta_state.itoi_r32g32b32.img_p_layout,
+ };
+
+ result = radv_CreateComputePipelines(radv_device_to_handle(device),
+ radv_pipeline_cache_to_handle(&device->meta_state.cache),
+ 1, &vk_pipeline_info, NULL,
+ &device->meta_state.itoi_r32g32b32.pipeline);
+
+fail:
+ ralloc_free(cs.nir);
+ return result;
+}
+
+static void
+radv_device_finish_meta_itoi_r32g32b32_state(struct radv_device *device)
+{
+ struct radv_meta_state *state = &device->meta_state;
+
+ radv_DestroyPipelineLayout(radv_device_to_handle(device),
+ state->itoi_r32g32b32.img_p_layout, &state->alloc);
+ radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
+ state->itoi_r32g32b32.img_ds_layout,
+ &state->alloc);
+ radv_DestroyPipeline(radv_device_to_handle(device),
+ state->itoi_r32g32b32.pipeline, &state->alloc);
+}
+
+static nir_shader *
+build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d)
+{
+ nir_builder b;
+ enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D;
+ const struct glsl_type *img_type = glsl_image_type(dim,
+ false,
+ GLSL_TYPE_FLOAT);
+ nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
+ b.shader->info.name = ralloc_strdup(b.shader, is_3d ? "meta_cleari_cs_3d" : "meta_cleari_cs");
+ b.shader->info.cs.local_size[0] = 16;
+ b.shader->info.cs.local_size[1] = 16;
+ b.shader->info.cs.local_size[2] = 1;
+
+ nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform,
+ img_type, "out_img");
+ output_img->data.descriptor_set = 0;
+ output_img->data.binding = 0;
+
+ nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
+ nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
+ nir_ssa_def *block_size = nir_imm_ivec4(&b,
+ b.shader->info.cs.local_size[0],
+ b.shader->info.cs.local_size[1],
+ b.shader->info.cs.local_size[2], 0);
+
+ nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
+
+ nir_intrinsic_instr *clear_val = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
+ nir_intrinsic_set_base(clear_val, 0);
+ nir_intrinsic_set_range(clear_val, 20);
+ clear_val->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
+ clear_val->num_components = 4;
+ nir_ssa_dest_init(&clear_val->instr, &clear_val->dest, 4, 32, "clear_value");
+ nir_builder_instr_insert(&b, &clear_val->instr);
+
+ nir_intrinsic_instr *layer = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
+ nir_intrinsic_set_base(layer, 0);
+ nir_intrinsic_set_range(layer, 20);
+ layer->src[0] = nir_src_for_ssa(nir_imm_int(&b, 16));
+ layer->num_components = 1;
+ nir_ssa_dest_init(&layer->instr, &layer->dest, 1, 32, "layer");
+ nir_builder_instr_insert(&b, &layer->instr);
+
+ nir_ssa_def *global_z = nir_iadd(&b, nir_channel(&b, global_id, 2), &layer->dest.ssa);
+
+ nir_ssa_def *comps[4];
+ comps[0] = nir_channel(&b, global_id, 0);
+ comps[1] = nir_channel(&b, global_id, 1);
+ comps[2] = global_z;
+ comps[3] = nir_imm_int(&b, 0);
+ global_id = nir_vec(&b, comps, 4);
+
+ nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
+ store->num_components = 4;
+ store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
+ store->src[1] = nir_src_for_ssa(global_id);
+ store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
+ store->src[3] = nir_src_for_ssa(&clear_val->dest.ssa);
+ store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
+
+ nir_builder_instr_insert(&b, &store->instr);
+ return b.shader;
+}
+
+static VkResult
+radv_device_init_meta_cleari_state(struct radv_device *device)
+{
+ VkResult result;
+ struct radv_shader_module cs = { .nir = NULL };
+ struct radv_shader_module cs_3d = { .nir = NULL };
+ cs.nir = build_nir_cleari_compute_shader(device, false);
+ if (device->physical_device->rad_info.chip_class >= GFX9)
+ cs_3d.nir = build_nir_cleari_compute_shader(device, true);
+
+ /*
+ * two descriptors one for the image being sampled
+ * one for the buffer being written.
+ */
+ VkDescriptorSetLayoutCreateInfo ds_create_info = {
+ .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
+ .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
+ .bindingCount = 1,
+ .pBindings = (VkDescriptorSetLayoutBinding[]) {
+ {
+ .binding = 0,
+ .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
+ .descriptorCount = 1,
+ .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
+ .pImmutableSamplers = NULL
+ },
+ }
+ };
+
+ result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
+ &ds_create_info,
+ &device->meta_state.alloc,
+ &device->meta_state.cleari.img_ds_layout);
+ if (result != VK_SUCCESS)
+ goto fail;
+
+
+ VkPipelineLayoutCreateInfo pl_create_info = {
+ .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
+ .setLayoutCount = 1,
+ .pSetLayouts = &device->meta_state.cleari.img_ds_layout,
+ .pushConstantRangeCount = 1,
+ .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 20},
+ };
+
+ result = radv_CreatePipelineLayout(radv_device_to_handle(device),
+ &pl_create_info,
+ &device->meta_state.alloc,
+ &device->meta_state.cleari.img_p_layout);
+ if (result != VK_SUCCESS)
+ goto fail;
+
+ /* compute shader */
+
+ VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
+ .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
+ .stage = VK_SHADER_STAGE_COMPUTE_BIT,
+ .module = radv_shader_module_to_handle(&cs),
+ .pName = "main",
+ .pSpecializationInfo = NULL,
+ };
+
+ VkComputePipelineCreateInfo vk_pipeline_info = {
+ .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
+ .stage = pipeline_shader_stage,
+ .flags = 0,
+ .layout = device->meta_state.cleari.img_p_layout,
+ };
+
+ result = radv_CreateComputePipelines(radv_device_to_handle(device),
+ radv_pipeline_cache_to_handle(&device->meta_state.cache),
+ 1, &vk_pipeline_info, NULL,
+ &device->meta_state.cleari.pipeline);
+ if (result != VK_SUCCESS)
+ goto fail;
+
+
+ if (device->physical_device->rad_info.chip_class >= GFX9) {
+ /* compute shader */
+ VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = {
+ .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
+ .stage = VK_SHADER_STAGE_COMPUTE_BIT,
+ .module = radv_shader_module_to_handle(&cs_3d),
+ .pName = "main",
+ .pSpecializationInfo = NULL,
+ };
+
+ VkComputePipelineCreateInfo vk_pipeline_info_3d = {
+ .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
+ .stage = pipeline_shader_stage_3d,
+ .flags = 0,
+ .layout = device->meta_state.cleari.img_p_layout,
+ };
+
+ result = radv_CreateComputePipelines(radv_device_to_handle(device),
+ radv_pipeline_cache_to_handle(&device->meta_state.cache),
+ 1, &vk_pipeline_info_3d, NULL,
+ &device->meta_state.cleari.pipeline_3d);
+ if (result != VK_SUCCESS)
+ goto fail;
+
+ ralloc_free(cs_3d.nir);
+ }
+ ralloc_free(cs.nir);
+ return VK_SUCCESS;
+fail:
+ ralloc_free(cs.nir);
+ ralloc_free(cs_3d.nir);
+ return result;
+}
+
+static void
+radv_device_finish_meta_cleari_state(struct radv_device *device)
+{
+ struct radv_meta_state *state = &device->meta_state;
+
+ radv_DestroyPipelineLayout(radv_device_to_handle(device),
+ state->cleari.img_p_layout, &state->alloc);
+ radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
+ state->cleari.img_ds_layout,
+ &state->alloc);
+ radv_DestroyPipeline(radv_device_to_handle(device),
+ state->cleari.pipeline, &state->alloc);
+ radv_DestroyPipeline(radv_device_to_handle(device),
+ state->cleari.pipeline_3d, &state->alloc);
+}
+
+/* Special path for clearing R32G32B32 images using a compute shader. */
+static nir_shader *
+build_nir_cleari_r32g32b32_compute_shader(struct radv_device *dev)
+{
+ nir_builder b;
+ const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_BUF,
+ false,
+ GLSL_TYPE_FLOAT);
+ nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
+ b.shader->info.name = ralloc_strdup(b.shader, "meta_cleari_r32g32b32_cs");
+ b.shader->info.cs.local_size[0] = 16;
+ b.shader->info.cs.local_size[1] = 16;
+ b.shader->info.cs.local_size[2] = 1;
+
+ nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform,
+ img_type, "out_img");
+ output_img->data.descriptor_set = 0;
+ output_img->data.binding = 0;
+
+ nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
+ nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32);
+ nir_ssa_def *block_size = nir_imm_ivec4(&b,
+ b.shader->info.cs.local_size[0],
+ b.shader->info.cs.local_size[1],
+ b.shader->info.cs.local_size[2], 0);
+
+ nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
+
+ nir_intrinsic_instr *clear_val = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
+ nir_intrinsic_set_base(clear_val, 0);
+ nir_intrinsic_set_range(clear_val, 16);
+ clear_val->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
+ clear_val->num_components = 3;
+ nir_ssa_dest_init(&clear_val->instr, &clear_val->dest, 3, 32, "clear_value");
+ nir_builder_instr_insert(&b, &clear_val->instr);
+
+ nir_intrinsic_instr *stride = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
+ nir_intrinsic_set_base(stride, 0);
+ nir_intrinsic_set_range(stride, 16);
+ stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 12));
+ stride->num_components = 1;
+ nir_ssa_dest_init(&stride->instr, &stride->dest, 1, 32, "stride");
+ nir_builder_instr_insert(&b, &stride->instr);
+
+ nir_ssa_def *global_x = nir_channel(&b, global_id, 0);
+ nir_ssa_def *global_y = nir_channel(&b, global_id, 1);
+
+ nir_ssa_def *global_pos =
+ nir_iadd(&b,
+ nir_imul(&b, global_y, &stride->dest.ssa),
+ nir_imul(&b, global_x, nir_imm_int(&b, 3)));
+
+ for (unsigned chan = 0; chan < 3; chan++) {
+ nir_ssa_def *local_pos =
+ nir_iadd(&b, global_pos, nir_imm_int(&b, chan));
+
+ nir_ssa_def *coord =
+ nir_vec4(&b, local_pos, local_pos, local_pos, local_pos);
+
+ nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
+ store->num_components = 1;
+ store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
+ store->src[1] = nir_src_for_ssa(coord);
+ store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
+ store->src[3] = nir_src_for_ssa(nir_channel(&b, &clear_val->dest.ssa, chan));
+ store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
+ nir_builder_instr_insert(&b, &store->instr);
+ }
+
+ return b.shader;
+}
+
+static VkResult
+radv_device_init_meta_cleari_r32g32b32_state(struct radv_device *device)
+{
+ VkResult result;
+ struct radv_shader_module cs = { .nir = NULL };
+
+ cs.nir = build_nir_cleari_r32g32b32_compute_shader(device);
+
+ VkDescriptorSetLayoutCreateInfo ds_create_info = {
+ .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
+ .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
+ .bindingCount = 1,
+ .pBindings = (VkDescriptorSetLayoutBinding[]) {
+ {
+ .binding = 0,
+ .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
+ .descriptorCount = 1,
+ .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
+ .pImmutableSamplers = NULL
+ },
+ }
+ };
+
+ result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
+ &ds_create_info,
+ &device->meta_state.alloc,
+ &device->meta_state.cleari_r32g32b32.img_ds_layout);
+ if (result != VK_SUCCESS)
+ goto fail;
+
+ VkPipelineLayoutCreateInfo pl_create_info = {
+ .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
+ .setLayoutCount = 1,
+ .pSetLayouts = &device->meta_state.cleari_r32g32b32.img_ds_layout,
+ .pushConstantRangeCount = 1,
+ .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
+ };
+
+ result = radv_CreatePipelineLayout(radv_device_to_handle(device),
+ &pl_create_info,
+ &device->meta_state.alloc,
+ &device->meta_state.cleari_r32g32b32.img_p_layout);
+ if (result != VK_SUCCESS)
+ goto fail;
+
+ /* compute shader */
+ VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
+ .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
+ .stage = VK_SHADER_STAGE_COMPUTE_BIT,
+ .module = radv_shader_module_to_handle(&cs),
+ .pName = "main",
+ .pSpecializationInfo = NULL,
+ };
+
+ VkComputePipelineCreateInfo vk_pipeline_info = {
+ .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
+ .stage = pipeline_shader_stage,
+ .flags = 0,
+ .layout = device->meta_state.cleari_r32g32b32.img_p_layout,
+ };
+
+ result = radv_CreateComputePipelines(radv_device_to_handle(device),
+ radv_pipeline_cache_to_handle(&device->meta_state.cache),
+ 1, &vk_pipeline_info, NULL,
+ &device->meta_state.cleari_r32g32b32.pipeline);
+
+fail:
+ ralloc_free(cs.nir);
+ return result;
+}
+
+static void
+radv_device_finish_meta_cleari_r32g32b32_state(struct radv_device *device)
+{
+ struct radv_meta_state *state = &device->meta_state;
+
+ radv_DestroyPipelineLayout(radv_device_to_handle(device),
+ state->cleari_r32g32b32.img_p_layout,
+ &state->alloc);
+ radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
+ state->cleari_r32g32b32.img_ds_layout,
+ &state->alloc);
+ radv_DestroyPipeline(radv_device_to_handle(device),
+ state->cleari_r32g32b32.pipeline, &state->alloc);
+}
+
+void
+radv_device_finish_meta_bufimage_state(struct radv_device *device)
+{
+ radv_device_finish_meta_itob_state(device);
+ radv_device_finish_meta_btoi_state(device);
+ radv_device_finish_meta_btoi_r32g32b32_state(device);
+ radv_device_finish_meta_itoi_state(device);
+ radv_device_finish_meta_itoi_r32g32b32_state(device);
+ radv_device_finish_meta_cleari_state(device);
+ radv_device_finish_meta_cleari_r32g32b32_state(device);
+}
+
+VkResult
+radv_device_init_meta_bufimage_state(struct radv_device *device)
+{
+ VkResult result;
+
+ result = radv_device_init_meta_itob_state(device);
+ if (result != VK_SUCCESS)
+ goto fail_itob;
+
+ result = radv_device_init_meta_btoi_state(device);
+ if (result != VK_SUCCESS)
+ goto fail_btoi;
+
+ result = radv_device_init_meta_btoi_r32g32b32_state(device);
+ if (result != VK_SUCCESS)
+ goto fail_btoi_r32g32b32;
+
+ result = radv_device_init_meta_itoi_state(device);
+ if (result != VK_SUCCESS)
+ goto fail_itoi;
+
+ result = radv_device_init_meta_itoi_r32g32b32_state(device);
+ if (result != VK_SUCCESS)
+ goto fail_itoi_r32g32b32;
+
+ result = radv_device_init_meta_cleari_state(device);
+ if (result != VK_SUCCESS)
+ goto fail_cleari;
+
+ result = radv_device_init_meta_cleari_r32g32b32_state(device);
+ if (result != VK_SUCCESS)
+ goto fail_cleari_r32g32b32;
+
+ return VK_SUCCESS;
+fail_cleari_r32g32b32:
+ radv_device_finish_meta_cleari_r32g32b32_state(device);
+fail_cleari:
+ radv_device_finish_meta_cleari_state(device);
+fail_itoi_r32g32b32:
+ radv_device_finish_meta_itoi_r32g32b32_state(device);
+fail_itoi:
+ radv_device_finish_meta_itoi_state(device);
+fail_btoi_r32g32b32:
+ radv_device_finish_meta_btoi_r32g32b32_state(device);
+fail_btoi:
+ radv_device_finish_meta_btoi_state(device);
+fail_itob:
+ radv_device_finish_meta_itob_state(device);
+ return result;
+}
+
+static void
+create_iview(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_meta_blit2d_surf *surf,
+ struct radv_image_view *iview)
+{
+ VkImageViewType view_type = cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 ? VK_IMAGE_VIEW_TYPE_2D :
+ radv_meta_get_view_type(surf->image);
+ radv_image_view_init(iview, cmd_buffer->device,
+ &(VkImageViewCreateInfo) {
+ .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
+ .image = radv_image_to_handle(surf->image),
+ .viewType = view_type,
+ .format = surf->format,
+ .subresourceRange = {
+ .aspectMask = surf->aspect_mask,
+ .baseMipLevel = surf->level,
+ .levelCount = 1,
+ .baseArrayLayer = surf->layer,
+ .layerCount = 1
+ },
+ }, NULL);
+}
+
+static void
+create_bview(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_buffer *buffer,