+ radv_update_dcc_metadata(cmd_buffer, image, range, true);
+
+ for (uint32_t l = 0; l < level_count; l++) {
+ uint64_t offset = image->offset + image->planes[0].surface.dcc_offset;
+ uint32_t level = range->baseMipLevel + l;
+ uint64_t size;
+
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+ /* Mipmap levels aren't implemented. */
+ assert(level == 0);
+ size = image->planes[0].surface.dcc_size;
+ } else {
+ const struct legacy_surf_level *surf_level =
+ &image->planes[0].surface.u.legacy.level[level];
+
+ /* If dcc_fast_clear_size is 0 (which might happens for
+ * mipmaps) the fill buffer operation below is a no-op.
+ * This can only happen during initialization as the
+ * fast clear path fallbacks to slow clears if one
+ * level can't be fast cleared.
+ */
+ offset += surf_level->dcc_offset +
+ surf_level->dcc_slice_fast_clear_size * range->baseArrayLayer;
+ size = surf_level->dcc_slice_fast_clear_size * radv_get_layerCount(image, range);
+ }
+
+ flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
+ size, value);
+ }
+
+ return flush_bits;
+}
+
+uint32_t
+radv_clear_htile(struct radv_cmd_buffer *cmd_buffer,
+ const struct radv_image *image,
+ const VkImageSubresourceRange *range,
+ uint32_t value)
+{
+ unsigned layer_count = radv_get_layerCount(image, range);
+ uint64_t size = image->planes[0].surface.htile_slice_size * layer_count;
+ uint64_t offset = image->offset + image->planes[0].surface.htile_offset +
+ image->planes[0].surface.htile_slice_size * range->baseArrayLayer;
+ uint32_t htile_mask, flush_bits;
+
+ htile_mask = radv_get_htile_mask(image, range->aspectMask);