+
+ if (nir->info.stage == MESA_SHADER_GEOMETRY) {
+ unsigned add_clip = nir->info.clip_distance_array_size +
+ nir->info.cull_distance_array_size > 4;
+ info->gs.gsvs_vertex_size =
+ (util_bitcount64(nir->info.outputs_written) + add_clip) * 16;
+ info->gs.max_gsvs_emit_size =
+ info->gs.gsvs_vertex_size * nir->info.gs.vertices_out;
+ }
+
+ /* Compute the ESGS item size for VS or TES as ES. */
+ if ((nir->info.stage == MESA_SHADER_VERTEX ||
+ nir->info.stage == MESA_SHADER_TESS_EVAL) &&
+ key->vs_common_out.as_es) {
+ struct radv_es_output_info *es_info =
+ nir->info.stage == MESA_SHADER_VERTEX ? &info->vs.es_info : &info->tes.es_info;
+
+ if (use_llvm) {
+ /* The outputs may contain gaps, use the highest output index + 1 */
+ uint32_t max_output_written = 0;
+ uint64_t output_mask = nir->info.outputs_written;
+
+ while (output_mask) {
+ const int i = u_bit_scan64(&output_mask);
+ unsigned param_index = shader_io_get_unique_index(i);
+
+ max_output_written = MAX2(param_index, max_output_written);
+ }
+ es_info->esgs_itemsize = (max_output_written + 1) * 16;
+ } else {
+ /* The outputs don't contain gaps, se we can use the number of outputs */
+ uint32_t num_outputs_written = nir->info.stage == MESA_SHADER_VERTEX
+ ? info->vs.num_linked_outputs
+ : info->tes.num_linked_outputs;
+ es_info->esgs_itemsize = num_outputs_written * 16;
+ }
+ }
+
+ info->float_controls_mode = nir->info.float_controls_execution_mode;
+
+ if (nir->info.stage == MESA_SHADER_FRAGMENT) {
+ /* If the i-th output is used, all previous outputs must be
+ * non-zero to match the target format.
+ * TODO: compact MRT to avoid holes and to remove this
+ * workaround.
+ */
+ unsigned num_targets = (util_last_bit(info->ps.cb_shader_mask) + 3) / 4;
+ for (unsigned i = 0; i < num_targets; i++) {
+ if (!(info->ps.cb_shader_mask & (0xf << (i * 4)))) {
+ info->ps.cb_shader_mask |= 0xf << (i * 4);
+ }
+ }
+
+ if (key->fs.is_dual_src) {
+ info->ps.cb_shader_mask |= (info->ps.cb_shader_mask & 0xf) << 4;
+ }
+ }