+
+ nir_deref_path_finish(&path);
+}
+
+static void
+gather_intrinsic_load_deref_info(const nir_shader *nir,
+ const nir_intrinsic_instr *instr,
+ struct radv_shader_info *info)
+{
+ switch (nir->info.stage) {
+ case MESA_SHADER_VERTEX: {
+ nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
+
+ if (var && var->data.mode == nir_var_shader_in) {
+ unsigned idx = var->data.location;
+ uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
+
+ info->vs.input_usage_mask[idx] |=
+ mask << var->data.location_frac;
+ }
+ break;
+ }
+ default:
+ break;
+ }
+}
+
+static uint32_t
+widen_writemask(uint32_t wrmask)
+{
+ uint32_t new_wrmask = 0;
+ for(unsigned i = 0; i < 4; i++)
+ new_wrmask |= (wrmask & (1 << i) ? 0x3 : 0x0) << (i * 2);
+ return new_wrmask;
+}
+
+static void
+set_output_usage_mask(const nir_shader *nir, const nir_intrinsic_instr *instr,
+ uint8_t *output_usage_mask)
+{
+ nir_deref_instr *deref_instr =
+ nir_instr_as_deref(instr->src[0].ssa->parent_instr);
+ nir_variable *var = nir_deref_instr_get_variable(deref_instr);
+ unsigned attrib_count = glsl_count_attribute_slots(deref_instr->type, false);
+ unsigned idx = var->data.location;
+ unsigned comp = var->data.location_frac;
+ unsigned const_offset = 0;
+
+ get_deref_offset(deref_instr, &const_offset);
+
+ if (var->data.compact) {
+ assert(!glsl_type_is_64bit(deref_instr->type));
+ const_offset += comp;
+ output_usage_mask[idx + const_offset / 4] |= 1 << (const_offset % 4);
+ return;
+ }
+
+ uint32_t wrmask = nir_intrinsic_write_mask(instr);
+ if (glsl_type_is_64bit(deref_instr->type))
+ wrmask = widen_writemask(wrmask);
+
+ for (unsigned i = 0; i < attrib_count; i++)
+ output_usage_mask[idx + i + const_offset] |=
+ ((wrmask >> (i * 4)) & 0xf) << comp;
+}
+
+static void
+gather_intrinsic_store_deref_info(const nir_shader *nir,
+ const nir_intrinsic_instr *instr,
+ struct radv_shader_info *info)
+{
+ nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
+
+ if (var && var->data.mode == nir_var_shader_out) {
+ unsigned idx = var->data.location;
+
+ switch (nir->info.stage) {
+ case MESA_SHADER_VERTEX:
+ set_output_usage_mask(nir, instr,
+ info->vs.output_usage_mask);
+ break;
+ case MESA_SHADER_GEOMETRY:
+ set_output_usage_mask(nir, instr,
+ info->gs.output_usage_mask);
+ break;
+ case MESA_SHADER_TESS_EVAL:
+ set_output_usage_mask(nir, instr,
+ info->tes.output_usage_mask);
+ break;
+ case MESA_SHADER_TESS_CTRL: {
+ unsigned param = shader_io_get_unique_index(idx);
+ const struct glsl_type *type = var->type;
+
+ if (!var->data.patch)
+ type = glsl_get_array_element(var->type);
+
+ unsigned slots =
+ var->data.compact ? DIV_ROUND_UP(var->data.location_frac + glsl_get_length(type), 4)
+ : glsl_count_attribute_slots(type, false);
+
+ mark_tess_output(info, var->data.patch, param, slots);
+ break;
+ }
+ default:
+ break;
+ }
+ }
+}
+
+static void
+gather_push_constant_info(const nir_shader *nir,
+ const nir_intrinsic_instr *instr,
+ struct radv_shader_info *info)
+{
+ int base = nir_intrinsic_base(instr);
+
+ if (!nir_src_is_const(instr->src[0])) {
+ info->has_indirect_push_constants = true;
+ } else {
+ uint32_t min = base + nir_src_as_uint(instr->src[0]);
+ uint32_t max = min + instr->num_components * 4;
+
+ info->max_push_constant_used =
+ MAX2(max, info->max_push_constant_used);
+ info->min_push_constant_used =
+ MIN2(min, info->min_push_constant_used);
+ }
+
+ if (instr->dest.ssa.bit_size != 32)
+ info->has_only_32bit_push_constants = false;
+
+ info->loads_push_constants = true;