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radv: add support for local bos. (v3)
[mesa.git]
/
src
/
amd
/
vulkan
/
winsys
/
amdgpu
/
radv_amdgpu_cs.c
diff --git
a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 46e5b7670331b640af0a76b87e9fc59ac8378bde..939c221e0c8c0b5c3587896c214f7607fa6a4810 100644
(file)
--- a/
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@
-202,7
+202,8
@@
radv_amdgpu_cs_create(struct radeon_winsys *ws,
if (cs->ws->use_ib_bos) {
cs->ib_buffer = ws->buffer_create(ws, ib_size, 0,
RADEON_DOMAIN_GTT,
if (cs->ws->use_ib_bos) {
cs->ib_buffer = ws->buffer_create(ws, ib_size, 0,
RADEON_DOMAIN_GTT,
- RADEON_FLAG_CPU_ACCESS);
+ RADEON_FLAG_CPU_ACCESS|
+ RADEON_FLAG_NO_INTERPROCESS_SHARING);
if (!cs->ib_buffer) {
free(cs);
return NULL;
if (!cs->ib_buffer) {
free(cs);
return NULL;
@@
-287,7
+288,8
@@
static void radv_amdgpu_cs_grow(struct radeon_winsys_cs *_cs, size_t min_size)
cs->ib_buffer = cs->ws->base.buffer_create(&cs->ws->base, ib_size, 0,
RADEON_DOMAIN_GTT,
cs->ib_buffer = cs->ws->base.buffer_create(&cs->ws->base, ib_size, 0,
RADEON_DOMAIN_GTT,
- RADEON_FLAG_CPU_ACCESS);
+ RADEON_FLAG_CPU_ACCESS|
+ RADEON_FLAG_NO_INTERPROCESS_SHARING);
if (!cs->ib_buffer) {
cs->base.cdw = 0;
if (!cs->ib_buffer) {
cs->base.cdw = 0;
@@
-471,6
+473,9
@@
static void radv_amdgpu_cs_add_buffer(struct radeon_winsys_cs *_cs,
return;
}
return;
}
+ if (bo->is_local)
+ return;
+
radv_amdgpu_cs_add_buffer_internal(cs, bo->bo, priority);
}
radv_amdgpu_cs_add_buffer_internal(cs, bo->bo, priority);
}
@@
-541,6
+546,10
@@
static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
} else if (count == 1 && !extra_bo && !extra_cs &&
!radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) {
struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[0];
} else if (count == 1 && !extra_bo && !extra_cs &&
!radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) {
struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[0];
+ if (cs->num_buffers == 0) {
+ *bo_list = 0;
+ return 0;
+ }
r = amdgpu_bo_list_create(ws->dev, cs->num_buffers, cs->handles,
cs->priorities, bo_list);
} else {
r = amdgpu_bo_list_create(ws->dev, cs->num_buffers, cs->handles,
cs->priorities, bo_list);
} else {
@@
-556,7
+565,10
@@
static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
if (extra_cs) {
total_buffer_count += ((struct radv_amdgpu_cs*)extra_cs)->num_buffers;
}
if (extra_cs) {
total_buffer_count += ((struct radv_amdgpu_cs*)extra_cs)->num_buffers;
}
-
+ if (total_buffer_count == 0) {
+ *bo_list = 0;
+ return 0;
+ }
amdgpu_bo_handle *handles = malloc(sizeof(amdgpu_bo_handle) * total_buffer_count);
uint8_t *priorities = malloc(sizeof(uint8_t) * total_buffer_count);
if (!handles || !priorities) {
amdgpu_bo_handle *handles = malloc(sizeof(amdgpu_bo_handle) * total_buffer_count);
uint8_t *priorities = malloc(sizeof(uint8_t) * total_buffer_count);
if (!handles || !priorities) {
@@
-721,7
+733,8
@@
static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
"see dmesg for more information.\n");
}
"see dmesg for more information.\n");
}
- amdgpu_bo_list_destroy(bo_list);
+ if (bo_list)
+ amdgpu_bo_list_destroy(bo_list);
if (fence)
radv_amdgpu_request_to_fence(ctx, fence, &request);
if (fence)
radv_amdgpu_request_to_fence(ctx, fence, &request);
@@
-795,7
+808,8
@@
static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
"see dmesg for more information.\n");
}
"see dmesg for more information.\n");
}
- amdgpu_bo_list_destroy(bo_list);
+ if (bo_list)
+ amdgpu_bo_list_destroy(bo_list);
if (r)
return r;
if (r)
return r;
@@
-856,7
+870,7
@@
static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
}
assert(cnt);
}
assert(cnt);
- bo = ws->buffer_create(ws, 4 * size, 4096, RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS);
+ bo = ws->buffer_create(ws, 4 * size, 4096, RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS
|RADEON_FLAG_NO_INTERPROCESS_SHARING
);
ptr = ws->buffer_map(bo);
if (preamble_cs) {
ptr = ws->buffer_map(bo);
if (preamble_cs) {
@@
-905,7
+919,8
@@
static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
"see dmesg for more information.\n");
}
"see dmesg for more information.\n");
}
- amdgpu_bo_list_destroy(bo_list);
+ if (bo_list)
+ amdgpu_bo_list_destroy(bo_list);
ws->buffer_destroy(bo);
if (r)
ws->buffer_destroy(bo);
if (r)
@@
-1038,7
+1053,8
@@
static struct radeon_winsys_ctx *radv_amdgpu_ctx_create(struct radeon_winsys *_w
assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * sizeof(uint64_t) <= 4096);
ctx->fence_bo = ws->base.buffer_create(&ws->base, 4096, 8,
RADEON_DOMAIN_GTT,
assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * sizeof(uint64_t) <= 4096);
ctx->fence_bo = ws->base.buffer_create(&ws->base, 4096, 8,
RADEON_DOMAIN_GTT,
- RADEON_FLAG_CPU_ACCESS);
+ RADEON_FLAG_CPU_ACCESS|
+ RADEON_FLAG_NO_INTERPROCESS_SHARING);
if (ctx->fence_bo)
ctx->fence_map = (uint64_t*)ws->base.buffer_map(ctx->fence_bo);
if (ctx->fence_map)
if (ctx->fence_bo)
ctx->fence_map = (uint64_t*)ws->base.buffer_map(ctx->fence_bo);
if (ctx->fence_map)