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hsail: Fix disassembly of load instruction with 3 destination operands
[gem5.git]
/
src
/
arch
/
x86
/
utility.cc
diff --git
a/src/arch/x86/utility.cc
b/src/arch/x86/utility.cc
index f7d0f816e1e4ed92f8f5d3c4ac29a91cb547fef1..cf30723487bb03eefb3b49f047e405b02b054ae2 100644
(file)
--- a/
src/arch/x86/utility.cc
+++ b/
src/arch/x86/utility.cc
@@
-183,7
+183,7
@@
void initCPU(ThreadContext *tc, int cpuId)
tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
Interrupts * interrupts = dynamic_cast<Interrupts *>(
tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
Interrupts * interrupts = dynamic_cast<Interrupts *>(
- tc->getCpuPtr()->getInterruptController());
+ tc->getCpuPtr()->getInterruptController(
0
));
assert(interrupts);
interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
assert(interrupts);
interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
@@
-217,11
+217,9
@@
copyMiscRegs(ThreadContext *src, ThreadContext *dest)
// need to be considered while copying state. That will likely not be
// true in the future.
for (int i = 0; i < NUM_MISCREGS; ++i) {
// need to be considered while copying state. That will likely not be
// true in the future.
for (int i = 0; i < NUM_MISCREGS; ++i) {
- if ( ( i != MISCREG_CR1 &&
- !(i > MISCREG_CR4 && i < MISCREG_CR8) &&
- !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
+ if (!isValidMiscReg(i))
continue;
continue;
- }
+
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
}
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
}